qiangdaqi.rar_VHDL抢答器_qiangdaqi_抢答器 VHDL_数字抢答器_计分抢答器

(3)抢答计分模块(JF.VHD) LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY JF IS PORT(RST: IN STD_LOGIC; ADD: IN STD_LOGIC; CHOSE: IN STD_LOGIC_VECTOR(3 DOWNTO 0); AA2,AA1,AA0,BB2,BB1,BB0: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); CC2,CC1,CC0,DD2,DD1,DD0: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END ENTITY JF; ARCHITECTURE ART OF JF IS BEGIN PROCESS(RST,ADD,CHOSE) IS VARIABLE A2,A1:STD_LOGIC_VECTOR(3 DOWNTO 0); VARIABLE B2,B1:STD_LOGIC_VECTOR(3 DOWNTO 0); VARIABLE C2,C1:STD_LOGIC_VECTOR(3 DOWNTO 0); VARIABLE D2,D1:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN IF(RST='1') THEN A2:="0001";A1:="0000"; B2:="0001";B1:="0000"; C2:="0001";C1:="0000"; D2:="0001";D1:="0000"; ELSIF(ADD'EVENT AND ADD='1') THEN IF CHOSE="0001" THEN IF A1="0001" THEN A1:="0000"; IF A2="1001" THEN A2:="0000"; ELSE A2:=A2+'1'; END IF; ELSE A1:=A1+'1'; END IF; ELSIF CHOSE="0010" THEN IF B1="1001" THEN B1:="0000"; IF B2="1001" THEN B2:="0000"; ELSE B2:=B2+'1'; END IF; ELSE B1:=B1+'1'; END IF; ELSIF CHOSE="0100" THEN IF C1="1001" THEN C1:="0000"; IF C2="1001" THEN C2:="0000"; ELSE C2:=C2+'1'; END IF; ELSE C1:=C1+'1'; END IF; ELSIF CHOSE="1000" THEN IF D1="1001" THEN D1:="0000"; IF D2="1001" THEN D2:="0000"; ELSE D2:=D2+'1'; END IF; ELSE D1:=D1+'1'; END IF; END IF; END IF; AA2<=A2;AA1<=A1;AA0<="0000"; BB2<=B2;BB1<=B1;BB0<="0000"; CC2<=C2;CC1<=C1;CC0<="0000"; DD2<=D2;DD1<=D1;DD0<="0000"; END PROCESS; END ARCHITECTURE ART;