Experiment 1: Write VHDL code for realize all logic gates.
a) AND Gate: A Logic circuit whose output is logic ‘1’ if and only if all of its inputs
are logic ‘1’.
Truth table Logic diagram
Y = A AND B
= A.B
VHDL Code for AND Gate:
-------------------------------------------------------------------------------
-- File : andgate.vhd
-- Entity : andgate
-------------------------------------------------------------------------------
-- University : Vishweswaraia Technological University
Belgaum,Karnataka
-- Simulators : Mentor Graphics Modelsim OR Active HDL
-- Synthesizers : Xilinx ISE
-- Target Device : XC4000 Series
-------------------------------------------------------------------------------
-- Description : VHDL code to realize AND gate functionality
-------------------------------------------------------------------------------
--The IEEE standard 1164 package, declares std_logic, etc.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
---------------------------------- Entity Declarations -------------------------
entity andgate is
Port( A : in std_logic;
B : in std_logic;
Y : out std_logic
);
end andgate;
architecture Behavioral of andgate is
begin
Y<= A and B ;
end Behavioral;
Inputs Output
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
AND2
1
2
3
A
Y
B
a
b
y
ns
500 1000 1500 2000 2500 3000
