sb_edac.rar_ddr4_ex_sb_edac.rar

/* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module * * This driver supports the memory controllers found on the Intel * processor family Sandy Bridge. * * This file may be distributed under the terms of the * GNU General Public License version 2 only. * * Copyright (c) 2011 by: * Mauro Carvalho Chehab */ #include <linux/module.h> #include <linux/init.h> #include <linux/pci.h> #include <linux/pci_ids.h> #include <linux/slab.h> #include <linux/delay.h> #include <linux/edac.h> #include <linux/mmzone.h> #include <linux/smp.h> #include <linux/bitmap.h> #include <linux/math64.h> #include <asm/processor.h> #include <asm/mce.h> #include "edac_core.h" /* Static vars */ static LIST_HEAD(sbridge_edac_list); static DEFINE_MUTEX(sbridge_edac_lock); static int probed; /* * Alter this version for the module when modifications are made */ #define SBRIDGE_REVISION " Ver: 1.1.0 " #define EDAC_MOD_STR "sbridge_edac" /* * Debug macros */ #define sbridge_printk(level, fmt, arg...) \ edac_printk(level, "sbridge", fmt, ##arg) #define sbridge_mc_printk(mci, level, fmt, arg...) \ edac_mc_chipset_printk(mci, level, "sbridge", fmt, ##arg) /* * Get a bit field at register value <v>, from bit <lo> to bit <hi> */ #define GET_BITFIELD(v, lo, hi) \ (((v) & GENMASK_ULL(hi, lo)) >> (lo)) /* Devices 12 Function 6, Offsets 0x80 to 0xcc */ static const u32 sbridge_dram_rule[] = { 0x80, 0x88, 0x90, 0x98, 0xa0, 0xa8, 0xb0, 0xb8, 0xc0, 0xc8, }; static const u32 ibridge_dram_rule[] = { 0x60, 0x68, 0x70, 0x78, 0x80, 0x88, 0x90, 0x98, 0xa0, 0xa8, 0xb0, 0xb8, 0xc0, 0xc8, 0xd0, 0xd8, 0xe0, 0xe8, 0xf0, 0xf8, }; #define SAD_LIMIT(reg) ((GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff) #define DRAM_ATTR(reg) GET_BITFIELD(reg, 2, 3) #define INTERLEAVE_MODE(reg) GET_BITFIELD(reg, 1, 1) #define DRAM_RULE_ENABLE(reg) GET_BITFIELD(reg, 0, 0) #define A7MODE(reg) GET_BITFIELD(reg, 26, 26) static char *get_dram_attr(u32 reg) { switch(DRAM_ATTR(reg)) { case 0: return "DRAM"; case 1: return "MMCFG"; case 2: return "NXM"; default: return "unknown"; } } static const u32 sbridge_interleave_list[] = { 0x84, 0x8c, 0x94, 0x9c, 0xa4, 0xac, 0xb4, 0xbc, 0xc4, 0xcc, }; static const u32 ibridge_interleave_list[] = { 0x64, 0x6c, 0x74, 0x7c, 0x84, 0x8c, 0x94, 0x9c, 0xa4, 0xac, 0xb4, 0xbc, 0xc4, 0xcc, 0xd4, 0xdc, 0xe4, 0xec, 0xf4, 0xfc, }; struct interleave_pkg { unsigned char start; unsigned char end; }; static const struct interleave_pkg sbridge_interleave_pkg[] = { { 0, 2 }, { 3, 5 }, { 8, 10 }, { 11, 13 }, { 16, 18 }, { 19, 21 }, { 24, 26 }, { 27, 29 }, }; static const struct interleave_pkg ibridge_interleave_pkg[] = { { 0, 3 }, { 4, 7 }, { 8, 11 }, { 12, 15 }, { 16, 19 }, { 20, 23 }, { 24, 27 }, { 28, 31 }, }; static inline int sad_pkg(const struct interleave_pkg *table, u32 reg, int interleave) { return GET_BITFIELD(reg, table[interleave].start, table[interleave].end); } /* Devices 12 Function 7 */ #define TOLM 0x80 #define TOHM 0x84 #define HASWELL_TOLM 0xd0 #define HASWELL_TOHM_0 0xd4 #define HASWELL_TOHM_1 0xd8 #define GET_TOLM(reg) ((GET_BITFIELD(reg, 0, 3) << 28) | 0x3ffffff) #define GET_TOHM(reg) ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff) /* Device 13 Function 6 */ #define SAD_TARGET 0xf0 #define SOURCE_ID(reg) GET_BITFIELD(reg, 9, 11) #define SAD_CONTROL 0xf4 /* Device 14 function 0 */ static const u32 tad_dram_rule[] = { 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c, 0x60, 0x64, 0x68, 0x6c, }; #define MAX_TAD ARRAY_SIZE(tad_dram_rule) #define TAD_LIMIT(reg) ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff) #define TAD_SOCK(reg) GET_BITFIELD(reg, 10, 11) #define TAD_CH(reg) GET_BITFIELD(reg, 8, 9) #define TAD_TGT3(reg) GET_BITFIELD(reg, 6, 7) #define TAD_TGT2(reg) GET_BITFIELD(reg, 4, 5) #define TAD_TGT1(reg) GET_BITFIELD(reg, 2, 3) #define TAD_TGT0(reg) GET_BITFIELD(reg, 0, 1) /* Device 15, function 0 */ #define MCMTR 0x7c #define IS_ECC_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 2, 2) #define IS_LOCKSTEP_ENABLED(mcmtr) GET_BITFIELD(mcmtr, 1, 1) #define IS_CLOSE_PG(mcmtr) GET_BITFIELD(mcmtr, 0, 0) /* Device 15, function 1 */ #define RASENABLES 0xac #define IS_MIRROR_ENABLED(reg) GET_BITFIELD(reg, 0, 0) /* Device 15, functions 2-5 */ static const int mtr_regs[] = { 0x80, 0x84, 0x88, }; #define RANK_DISABLE(mtr) GET_BITFIELD(mtr, 16, 19) #define IS_DIMM_PRESENT(mtr) GET_BITFIELD(mtr, 14, 14) #define RANK_CNT_BITS(mtr) GET_BITFIELD(mtr, 12, 13) #define RANK_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 2, 4) #define COL_WIDTH_BITS(mtr) GET_BITFIELD(mtr, 0, 1) static const u32 tad_ch_nilv_offset[] = { 0x90, 0x94, 0x98, 0x9c, 0xa0, 0xa4, 0xa8, 0xac, 0xb0, 0xb4, 0xb8, 0xbc, }; #define CHN_IDX_OFFSET(reg) GET_BITFIELD(reg, 28, 29) #define TAD_OFFSET(reg) (GET_BITFIELD(reg, 6, 25) << 26) static const u32 rir_way_limit[] = { 0x108, 0x10c, 0x110, 0x114, 0x118, }; #define MAX_RIR_RANGES ARRAY_SIZE(rir_way_limit) #define IS_RIR_VALID(reg) GET_BITFIELD(reg, 31, 31) #define RIR_WAY(reg) GET_BITFIELD(reg, 28, 29) #define MAX_RIR_WAY 8 static const u32 rir_offset[MAX_RIR_RANGES][MAX_RIR_WAY] = { { 0x120, 0x124, 0x128, 0x12c, 0x130, 0x134, 0x138, 0x13c }, { 0x140, 0x144, 0x148, 0x14c, 0x150, 0x154, 0x158, 0x15c }, { 0x160, 0x164, 0x168, 0x16c, 0x170, 0x174, 0x178, 0x17c }, { 0x180, 0x184, 0x188, 0x18c, 0x190, 0x194, 0x198, 0x19c }, { 0x1a0, 0x1a4, 0x1a8, 0x1ac, 0x1b0, 0x1b4, 0x1b8, 0x1bc }, }; #define RIR_RNK_TGT(reg) GET_BITFIELD(reg, 16, 19) #define RIR_OFFSET(reg) GET_BITFIELD(reg, 2, 14) /* Device 16, functions 2-7 */ /* * FIXME: Implement the error count reads directly */ static const u32 correrrcnt[] = { 0x104, 0x108, 0x10c, 0x110, }; #define RANK_ODD_OV(reg) GET_BITFIELD(reg, 31, 31) #define RANK_ODD_ERR_CNT(reg) GET_BITFIELD(reg, 16, 30) #define RANK_EVEN_OV(reg) GET_BITFIELD(reg, 15, 15) #define RANK_EVEN_ERR_CNT(reg) GET_BITFIELD(reg, 0, 14) static const u32 correrrthrsld[] = { 0x11c, 0x120, 0x124, 0x128, }; #define RANK_ODD_ERR_THRSLD(reg) GET_BITFIELD(reg, 16, 30) #define RANK_EVEN_ERR_THRSLD(reg) GET_BITFIELD(reg, 0, 14) /* Device 17, function 0 */ #define SB_RANK_CFG_A 0x0328 #define IB_RANK_CFG_A 0x0320 /* * sbridge structs */ #define NUM_CHANNELS 4 #define MAX_DIMMS 3 /* Max DIMMS per channel */ #define CHANNEL_UNSPECIFIED 0xf /* Intel IA32 SDM 15-14 */ enum type { SANDY_BRIDGE, IVY_BRIDGE, HASWELL, BROADWELL, }; struct sbridge_pvt; struct sbridge_info { enum type type; u32 mcmtr; u32 rankcfgr; u64 (*get_tolm)(struct sbridge_pvt *pvt); u64 (*get_tohm)(struct sbridge_pvt *pvt); u64 (*rir_limit)(u32 reg); const u32 *dram_rule; const u32 *interleave_list; const struct interleave_pkg *interleave_pkg; u8 max_sad; u8 max_interleave; u8 (*get_node_id)(struct sbridge_pvt *pvt); enum mem_type (*get_memory_type)(struct sbridge_pvt *pvt); struct pci_dev *pci_vtd; }; struct sbridge_channel { u32 ranks; u32 dimms; }; struct pci_id_descr { int dev_id; int optional; }; struct pci_id_table { const struct pci_id_descr *descr; int n_devs; }; struct sbridge_dev { struct list_head list; u8 bus, mc; u8 node_id, source_id; struct pci_dev **pdev; int n_devs; struct mem_ctl_info *mci; }; struct sbridge_pvt { struct pci_dev *pci_ta, *pci_ddrio, *pci_ras; struct pci_dev *pci_sad0, *pci_sad1; struct pci_dev *pci_ha0, *pci_ha1; struct pci_dev *pci_br0, *pci_br1; struct pci_dev *pci_ha1_ta; struct pci_dev *pci_tad[NUM_CHANNELS]; struct sbridge_dev *sbridge_dev; struct sbridge_info info; struct sbridge_channel channel[NUM_CHANNELS]; /* Memory type detection */ bool is_mirrored, is_lockstep, is_close_pg; /* Fifo double buffers */ struct mce mce_entry[MCE_LOG_LEN]; struct mce mce_outentry[MCE_LOG_LEN]; /* Fifo in/out counters */ unsigned mce_in, mce_out; /* Count indicator to show errors not got */ unsigned mce_overrun; /* Me