mpc85xx_edac.rar_memory

/* * Freescale MPC85xx Memory Controller kenel module * * Author: Dave Jiang <djiang@mvista.com> * * 2006-2007 (c) MontaVista Software, Inc. This file is licensed under * the terms of the GNU General Public License version 2. This program * is licensed "as is" without any warranty of any kind, whether express * or implied. * */ #include <linux/module.h> #include <linux/init.h> #include <linux/interrupt.h> #include <linux/ctype.h> #include <linux/io.h> #include <linux/mod_devicetable.h> #include <linux/edac.h> #include <linux/smp.h> #include <linux/gfp.h> #include <linux/of_platform.h> #include <linux/of_device.h> #include "edac_module.h" #include "edac_core.h" #include "mpc85xx_edac.h" static int edac_dev_idx; #ifdef CONFIG_PCI static int edac_pci_idx; #endif static int edac_mc_idx; static u32 orig_ddr_err_disable; static u32 orig_ddr_err_sbe; /* * PCI Err defines */ #ifdef CONFIG_PCI static u32 orig_pci_err_cap_dr; static u32 orig_pci_err_en; #endif static u32 orig_l2_err_disable; #ifdef CONFIG_FSL_SOC_BOOKE static u32 orig_hid1[2]; #endif /************************ MC SYSFS parts ***********************************/ #define to_mci(k) container_of(k, struct mem_ctl_info, dev) static ssize_t mpc85xx_mc_inject_data_hi_show(struct device *dev, struct device_attribute *mattr, char *data) { struct mem_ctl_info *mci = to_mci(dev); struct mpc85xx_mc_pdata *pdata = mci->pvt_info; return sprintf(data, "0x%08x", in_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_HI)); } static ssize_t mpc85xx_mc_inject_data_lo_show(struct device *dev, struct device_attribute *mattr, char *data) { struct mem_ctl_info *mci = to_mci(dev); struct mpc85xx_mc_pdata *pdata = mci->pvt_info; return sprintf(data, "0x%08x", in_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_LO)); } static ssize_t mpc85xx_mc_inject_ctrl_show(struct device *dev, struct device_attribute *mattr, char *data) { struct mem_ctl_info *mci = to_mci(dev); struct mpc85xx_mc_pdata *pdata = mci->pvt_info; return sprintf(data, "0x%08x", in_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT)); } static ssize_t mpc85xx_mc_inject_data_hi_store(struct device *dev, struct device_attribute *mattr, const char *data, size_t count) { struct mem_ctl_info *mci = to_mci(dev); struct mpc85xx_mc_pdata *pdata = mci->pvt_info; if (isdigit(*data)) { out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_HI, simple_strtoul(data, NULL, 0)); return count; } return 0; } static ssize_t mpc85xx_mc_inject_data_lo_store(struct device *dev, struct device_attribute *mattr, const char *data, size_t count) { struct mem_ctl_info *mci = to_mci(dev); struct mpc85xx_mc_pdata *pdata = mci->pvt_info; if (isdigit(*data)) { out_be32(pdata->mc_vbase + MPC85XX_MC_DATA_ERR_INJECT_LO, simple_strtoul(data, NULL, 0)); return count; } return 0; } static ssize_t mpc85xx_mc_inject_ctrl_store(struct device *dev, struct device_attribute *mattr, const char *data, size_t count) { struct mem_ctl_info *mci = to_mci(dev); struct mpc85xx_mc_pdata *pdata = mci->pvt_info; if (isdigit(*data)) { out_be32(pdata->mc_vbase + MPC85XX_MC_ECC_ERR_INJECT, simple_strtoul(data, NULL, 0)); return count; } return 0; } DEVICE_ATTR(inject_data_hi, S_IRUGO | S_IWUSR, mpc85xx_mc_inject_data_hi_show, mpc85xx_mc_inject_data_hi_store); DEVICE_ATTR(inject_data_lo, S_IRUGO | S_IWUSR, mpc85xx_mc_inject_data_lo_show, mpc85xx_mc_inject_data_lo_store); DEVICE_ATTR(inject_ctrl, S_IRUGO | S_IWUSR, mpc85xx_mc_inject_ctrl_show, mpc85xx_mc_inject_ctrl_store); static int mpc85xx_create_sysfs_attributes(struct mem_ctl_info *mci) { int rc; rc = device_create_file(&mci->dev, &dev_attr_inject_data_hi); if (rc < 0) return rc; rc = device_create_file(&mci->dev, &dev_attr_inject_data_lo); if (rc < 0) return rc; rc = device_create_file(&mci->dev, &dev_attr_inject_ctrl); if (rc < 0) return rc; return 0; } static void mpc85xx_remove_sysfs_attributes(struct mem_ctl_info *mci) { device_remove_file(&mci->dev, &dev_attr_inject_data_hi); device_remove_file(&mci->dev, &dev_attr_inject_data_lo); device_remove_file(&mci->dev, &dev_attr_inject_ctrl); } /**************************** PCI Err device ***************************/ #ifdef CONFIG_PCI static void mpc85xx_pci_check(struct edac_pci_ctl_info *pci) { struct mpc85xx_pci_pdata *pdata = pci->pvt_info; u32 err_detect; err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR); /* master aborts can happen during PCI config cycles */ if (!(err_detect & ~(PCI_EDE_MULTI_ERR | PCI_EDE_MST_ABRT))) { out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect); return; } printk(KERN_ERR "PCI error(s) detected\n"); printk(KERN_ERR "PCI/X ERR_DR register: %#08x\n", err_detect); printk(KERN_ERR "PCI/X ERR_ATTRIB register: %#08x\n", in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ATTRIB)); printk(KERN_ERR "PCI/X ERR_ADDR register: %#08x\n", in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_ADDR)); printk(KERN_ERR "PCI/X ERR_EXT_ADDR register: %#08x\n", in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EXT_ADDR)); printk(KERN_ERR "PCI/X ERR_DL register: %#08x\n", in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DL)); printk(KERN_ERR "PCI/X ERR_DH register: %#08x\n", in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DH)); /* clear error bits */ out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR, err_detect); if (err_detect & PCI_EDE_PERR_MASK) edac_pci_handle_pe(pci, pci->ctl_name); if ((err_detect & ~PCI_EDE_MULTI_ERR) & ~PCI_EDE_PERR_MASK) edac_pci_handle_npe(pci, pci->ctl_name); } static irqreturn_t mpc85xx_pci_isr(int irq, void *dev_id) { struct edac_pci_ctl_info *pci = dev_id; struct mpc85xx_pci_pdata *pdata = pci->pvt_info; u32 err_detect; err_detect = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_DR); if (!err_detect) return IRQ_NONE; mpc85xx_pci_check(pci); return IRQ_HANDLED; } int mpc85xx_pci_err_probe(struct platform_device *op) { struct edac_pci_ctl_info *pci; struct mpc85xx_pci_pdata *pdata; struct resource r; int res = 0; if (!devres_open_group(&op->dev, mpc85xx_pci_err_probe, GFP_KERNEL)) return -ENOMEM; pci = edac_pci_alloc_ctl_info(sizeof(*pdata), "mpc85xx_pci_err"); if (!pci) return -ENOMEM; /* make sure error reporting method is sane */ switch (edac_op_state) { case EDAC_OPSTATE_POLL: case EDAC_OPSTATE_INT: break; default: edac_op_state = EDAC_OPSTATE_INT; break; } pdata = pci->pvt_info; pdata->name = "mpc85xx_pci_err"; pdata->irq = NO_IRQ; dev_set_drvdata(&op->dev, pci); pci->dev = &op->dev; pci->mod_name = EDAC_MOD_STR; pci->ctl_name = pdata->name; pci->dev_name = dev_name(&op->dev); if (edac_op_state == EDAC_OPSTATE_POLL) pci->edac_check = mpc85xx_pci_check; pdata->edac_idx = edac_pci_idx++; res = of_address_to_resource(op->dev.of_node, 0, &r); if (res) { printk(KERN_ERR "%s: Unable to get resource for " "PCI err regs\n", __func__); goto err; } /* we only need the error registers */ r.start += 0xe00; if (!devm_request_mem_region(&op->dev, r.start, resource_size(&r), pdata->name)) { printk(KERN_ERR "%s: Error while requesting mem region\n", __func__); res = -EBUSY; goto err; } pdata->pci_vbase = devm_ioremap(&op->dev, r.start, resource_size(&r)); if (!pdata->pci_vbase) { printk(KERN_ERR "%s: Unable to setup PCI err regs\n", __func__); res = -ENOMEM; goto err; } orig_pci_err_cap_dr = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR); /* PCI master abort is expected during config cycles */ out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_CAP_DR, 0x40); orig_pci_err_en = in_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN); /* disable master abort reporting */ out_be32(pdata->pci_vbase + MPC85XX_PCI_ERR_EN, ~0x40); /* clear error bits