The
VHDL
Golden
Reference
Guide
DOULOS
DOULOS
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© Copyright 1995, Doulos, All Rights Reserved.
No part of this publication may be reproduced, stored in a retrieval
system, or transmitted, in any form or by any means, electronic,
mechanical, photocopying, recording or otherwise, without the
prior written permission of DOULOS. Printed in the United
Kingdom of Great Britain and Northern Ireland.
Version 1.1, December 1995
The VHDL Golden Reference Guide is a compact quick reference
guide to the VHDL language, its syntax, semantics, synthesis and
application to hardware design.
The VHDL Golden Reference Guide is not intended as a replacement
for the IEEE Standard VHDL Language Reference Manual. Unlike
that document, the Golden Reference guide does not offer a
complete, formal description of VHDL. Rather, it offers answers to
the questions most often asked during the practical application of
VHDL, in a convenient reference format.
Nor is The VHDL Golden Reference Guide intended to be an
introductory tutorial. Information is presented here in a terse
reference format, not in the progressive and sympathetic manner
necessary to learn a subject as complex as VHDL. However,
acknowledging that those already familiar with computer languages
may wish to use this guide as a VHDL text book, a brief informal
introduction to the subject is given at the start.
The main feature of The VHDL Golden Reference Guide is that it
embodies much practical wisdom gathered over many VHDL
projects. It does not only provide a handy syntax reference; there are
many similar books which perform that task adequately. It also
warns you of the most common language errors, gives clues where
to look when your code will not compile, alerts you to synthesis
issues, and gives advice on improving your coding style.
The VHDL Golden Reference Guide was developed to add value to
the Doulos range of VHDL training courses, and also to complement
VHDL PaceMaker, the VHDL Computer Based Training package
from Doulos.
3
Preface
The main body of this guide is organised alphabetically. Each section
is indexed by a key term which appears prominently at the top of
each page. Often you can find the information you want by flicking
through the guide looking for the appropriate key term. If that fails,
there is a full index at the back.
Most of the information in this guide is organised around the VHDL
syntax headings, but there are additional special sections on Coding
Standards, Design Flow, Errors, Reserved Words and VHDL 93, and
also listings of the standard packages Standard, TEXTIO,
Std_logic_1164 and Numeric_std.
If you are new to VHDL, you should start by reading A Brief
Introduction to VHDL, which follows overleaf.
The Index
Bold index entries have corresponding pages in the main alphabetical
reference section. The remaining index entries are followed by a list
of appropriate page references in the main alphabetical reference
section, given in order of importance.
Key To Notation Used To Define VHDL Syntax
The syntax definitions are written to look like examples whereever
possible, but it has been necessary to introduce some extra notation.
In brief, square brackets [] enclose optional items, three dots ... means
repetition, and curly brackets {} enclose comments. ItalicNames
represent parts of the syntax defined elsewhere. A full description of
the notation follows:
Curly brackets {} enclose comments that are not part of the VHDL
syntax being defined, but give you further information about the
syntax definition.
Syntax enclosed in square brackets [] is optional (except in the
definition of a signature, where square brackets are part of the VHDL
syntax!)
... means zero or more repetitions of the preceding item or line, or
means a list, as follows:
Item ... means zero or more repetitions of the Item.
, ... means repeat in a comma separated list (e.g. A, B, C).
; ... means repeat in a semicolon separated list.
| ... means repeat in a bar separated list.
4
Using This Guide
There must be at least one item in the list. There is no , ; or | at the
end of the list, unless it is given explicitly (as in ; ... ; ).
Underlined syntax
belongs to the VHDL'93 language, but not to
VHDL'87. (For the sake of clarity, underlining has been omitted
where words contain the underscore character.)
words in lower case letters are reserved words, built into the VHDL
language (e.g. entity)
Capitalised Words (not in italics) are VHDL identifiers, i.e. user
defined or pre-defined names that are not reserved identifiers (e.g.
TypeName, BlockLabel).
Italic Words are syntactic categories, i.e. the name of a syntax
definition given in full elsewhere. A syntactic category can be either
defined on the same page, defined on a separate page, or one of the
two special categories defined below.
Italics = indicates a syntactic category which is defined and used on
the same page.
Special syntactic categories:
SomethingExpression = Expression, where the Something gives
information about the meaning of the expression (e.g.
TimeExpression).
Condition = Expression, where the type of the expression is Boolean.
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