Copyright © 2008-2010 ARM. All rights reserved.
ARM DDI 0407F (ID050110)
Cortex
™
-A9 MPCore
Revision: r2p2
Technical Reference Manual
ii Copyright © 2008-2010 ARM. All rights reserved. ARM DDI 0407F
Non-Confidential ID050110
Cortex-A9 MPCore
Technical Reference Manual
Copyright © 2008-2010 ARM. All rights reserved.
Release Information
The following changes have been made to this book.
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Change history
Date Issue Confidentiality Change
04 April 2008 A Non-Confidential First release for r0p0
08 July 2008 B Non-Confidential Restricted Access First release for r0p1
16 December 2008 C Non-Confidential Restricted Access First release for r1p0
2 October 2009 D Non-Confidential Restricted Access First release for r2p0
27 November 2009 E Non-Confidential Unrestricted Access Second release for r2p0
30 April 2010 F Non-Confidential Unrestricted Access First release for r2p2
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Contents
Cortex-A9 MPCore Technical Reference Manual
Preface
About this manual ........................................................................................ xiv
Additional reading ....................................................................................... xvii
Feedback ..................................................................................................... xix
Chapter 1 Introduction
1.1 About the Cortex-A9 MPCore processor ..................................................... 1-2
1.2 Configurable options ................................................................................... 1-4
1.3 Private Memory Region ............................................................................... 1-5
1.4 Interfaces .................................................................................................... 1-7
1.5 MPCore considerations ............................................................................... 1-8
1.6 Product revisions ...................................................................................... 1-10
Chapter 2 Snoop Control Unit
2.1 About the SCU ............................................................................................ 2-2
2.2 SCU registers .............................................................................................. 2-3
2.3 AMBA AXI Master Port Interfaces ............................................................. 2-15
2.4 Accelerator Coherency Port ...................................................................... 2-24
2.5 Event communication with an external agent using WFE/SEV ................. 2-27
