Copyright © 2005, 2006 ARM Limited. All rights reserved.
ARM DDI 0337B
Cortex-M3
™
Revision: r0p0
Technical Reference Manual
ii
Copyright © 2005, 2006 ARM Limited. All rights reserved.
ARM DDI 0337B
Cortex-M3
Technical Reference Manual
Copyright © 2005, 2006 ARM Limited. All rights reserved.
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Date Issue Confidentiality Change
15 December 2005 A Confidential First Release
13 January 2006 B Non-Confidential Confidentiality status amended
ARM DDI 0337B
Copyright © 2005, 2006 ARM Limited. All rights reserved.
iii
Contents
Cortex-M3 Technical Reference Manual
Preface
About this manual ...................................................................................... xviii
Feedback ................................................................................................... xxiii
Chapter 1 Introduction
1.1 About the processor .................................................................................... 1-2
1.2 Components of the processor ..................................................................... 1-4
1.3 Configurable options ................................................................................. 1-12
1.4 Instruction set summary ............................................................................ 1-13
Chapter 2 Programmer’s Model
2.1 About the programmer’s model ................................................................... 2-2
2.2 Privileged access and User access ............................................................ 2-3
2.3 Registers ..................................................................................................... 2-4
2.4 Data types ................................................................................................. 2-10
2.5 Memory formats ........................................................................................ 2-11
2.6 Instruction set ............................................................................................ 2-13
Chapter 3 System Control
3.1 Summary of processor registers ................................................................. 3-2
Contents
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Copyright © 2005, 2006 ARM Limited. All rights reserved.
ARM DDI 0337B
Chapter 4 Memory Map
4.1 About the memory map .............................................................................. 4-2
4.2 Bit-banding ................................................................................................. 4-5
4.3 ROM memory table .................................................................................... 4-8
Chapter 5 Exceptions
5.1 About the exception model ......................................................................... 5-2
5.2 Exception types .......................................................................................... 5-3
5.3 Exception priority ........................................................................................ 5-5
5.4 Privilege and stacks .................................................................................... 5-8
5.5 Pre-emption .............................................................................................. 5-10
5.6 Tail-chaining ............................................................................................. 5-13
5.7 Late-arriving .............................................................................................. 5-14
5.8 Exit ............................................................................................................ 5-16
5.9 Resets ...................................................................................................... 5-19
5.10 Exception control transfer ......................................................................... 5-23
5.11 Setting up multiple stacks ......................................................................... 5-24
5.12 Abort model .............................................................................................. 5-26
5.13 Activation levels ........................................................................................ 5-31
5.14 Flowcharts ................................................................................................ 5-33
Chapter 6 Clocking and Resets
6.1 Cortex-M3 clocking ..................................................................................... 6-2
6.2 Cortex-M3 resets ........................................................................................ 6-4
6.3 Cortex-M3 reset modes .............................................................................. 6-5
Chapter 7 Power Management
7.1 About power management ......................................................................... 7-2
7.2 System power management ....................................................................... 7-3
Chapter 8 Nested Vectored Interrupt Controller
8.1 About the NVIC ........................................................................................... 8-2
8.2 NVIC programmer’s model ......................................................................... 8-3
8.3 Level versus pulse interrupts .................................................................... 8-39
Chapter 9 Memory Protection Unit
9.1 About the MPU ........................................................................................... 9-2
9.2 MPU programmer’s model .......................................................................... 9-3
9.3 MPU access permissions ......................................................................... 9-14
9.4 MPU aborts ............................................................................................... 9-16
9.5 Updating an MPU region .......................................................................... 9-17
9.6 Interrupts and updating the MPU .............................................................. 9-20
Chapter 10 Core Debug
10.1 About core debug ..................................................................................... 10-2
Contents
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10.2 Core debug registers ................................................................................ 10-3
10.3 Core debug access example .................................................................. 10-12
10.4 Using application registers in core debug ............................................... 10-13
Chapter 11 System Debug
11.1 About system debug ................................................................................. 11-2
11.2 System Debug Access .............................................................................. 11-3
11.3 System debug programmer’s model ......................................................... 11-5
11.4 Flash Patch and Breakpoint ...................................................................... 11-6
11.5 Data Watchpoint and Trace .................................................................... 11-13
11.6 Instrumentation Trace Macrocell ............................................................. 11-28
11.7 AHB Access Port .................................................................................... 11-37
Chapter 12 Debug Port
12.1 About the Debug Port ............................................................................... 12-2
12.2 JTAG-DP ................................................................................................... 12-3
12.3 SW-DP .................................................................................................... 12-20
12.4 Common Debug Port (DP) features ........................................................ 12-41
12.5 Debug Port Programmer’s Model ............................................................ 12-47
Chapter 13 Trace Port Interface Unit
13.1 About the Trace Port Interface Unit .......................................................... 13-2
13.2 TPIU registers ........................................................................................... 13-8
Chapter 14 Bus Interface
14.1 About bus interfaces ................................................................................. 14-2
14.2 ICode bus interface ................................................................................... 14-3
14.3 DCode bus interface ................................................................................. 14-5
14.4 System interface ....................................................................................... 14-6
14.5 External private peripheral interface ......................................................... 14-8
14.6 Access alignment ...................................................................................... 14-9
14.7 Unaligned accesses that cross regions ................................................... 14-10
14.8 Bit-band accesses ................................................................................... 14-11
14.9 Write buffer ............................................................................................. 14-12
14.10 Memory attributes ................................................................................... 14-13
Chapter 15 Embedded Trace Macrocell
15.1 About the ETM .......................................................................................... 15-2
15.2 Data tracing ............................................................................................... 15-6
15.3 ETM Resources ........................................................................................ 15-7
15.4 Trace output .............................................................................................. 15-9
15.5 ETM architecture ..................................................................................... 15-10
15.6 ETM programmer’s model ....................................................................... 15-14
Chapter 16 Embedded Trace Macrocell Interface
16.1 About the ETM interface ........................................................................... 16-2
