Contents
ARM DDI 0464F Copyright © 2011-2013 ARM. All rights reserved. iv
ID051113 Non-Confidential
3.9 Memory model ....................................................................................................... 3-11
Chapter 4 System Control
4.1 About system control ............................................................................................... 4-2
4.2 Register summary .................................................................................................... 4-3
4.3 Register descriptions ............................................................................................. 4-26
Chapter 5 Memory Management Unit
5.1 About the MMU ........................................................................................................ 5-2
5.2 Memory management system ................................................................................. 5-3
5.3 TLB organization ...................................................................................................... 5-5
5.4 TLB match process .................................................................................................. 5-6
5.5 Memory access sequence ....................................................................................... 5-7
5.6 MMU enabling and disabling ................................................................................... 5-8
5.7 External aborts ......................................................................................................... 5-9
5.8 MMU software accessible registers ....................................................................... 5-10
Chapter 6 L1 Memory System
6.1 About the L1 memory system .................................................................................. 6-2
6.2 Cache behavior ........................................................................................................ 6-3
6.3 L1 instruction memory system ................................................................................. 6-4
6.4 L1 data memory system .......................................................................................... 6-6
6.5 Data prefetching ...................................................................................................... 6-8
6.6 Direct access to internal memory ............................................................................ 6-9
Chapter 7 L2 Memory System
7.1 About the L2 Memory system .................................................................................. 7-2
7.2 Snoop Control Unit .................................................................................................. 7-3
7.3 Master interface ....................................................................................................... 7-5
7.4 Optional integrated L2 cache ................................................................................. 7-10
7.5 AXI privilege information ........................................................................................ 7-11
Chapter 8 Generic Interrupt Controller
8.1 About the GIC .......................................................................................................... 8-2
8.2 GIC functional description ........................................................................................ 8-3
8.3 GIC programmers model ......................................................................................... 8-6
Chapter 9 Generic Timer
9.1 About the Generic Timer .......................................................................................... 9-2
9.2 Generic timer functional description ........................................................................ 9-3
9.3 Timer programmers model ...................................................................................... 9-4
Chapter 10 Debug
10.1 About debug .......................................................................................................... 10-2
10.2 Debug register interfaces ....................................................................................... 10-4
10.3 Debug register summary ....................................................................................... 10-5
10.4 Debug register descriptions ................................................................................... 10-9
10.5 Debug events ....................................................................................................... 10-33
10.6 External debug interface ...................................................................................... 10-34
Chapter 11 Performance Monitoring Unit
11.1 About the Performance Monitoring Unit ................................................................. 11-2
11.2 PMU functional description .................................................................................... 11-3
11.3 PMU registers summary ........................................................................................ 11-4
11.4 PMU register descriptions ...................................................................................... 11-7
11.5 Events .................................................................................................................. 11-10
11.6 Interrupts .............................................................................................................. 11-12
11.7 Exporting PMU events ......................................................................................... 11-13
