没有合适的资源？快使用搜索试试~ 我知道了~
温馨提示
文档标题中指出了文件是《Cortex-A7 MPCore 技术参考手册》，这是一份由ARM公司发布的技术文档，其中Cortex-A7 MPCore指的是ARM设计的多核处理器Cortex-A7的多核版本。"MPCore"通常表示该处理器具备多核处理能力，意味着可以在单个芯片上集成多个Cortex-A7处理核心，以提高计算性能。 文档描述中提到，这份手册的版本为r0p5，且文档内容的版权归ARM公司所有，首次发布是在2011年，并且在此后的几年内陆续发布了多个版本（r0p0至r0p5），显示出该技术文档以及对应的处理器技术在不断完善和发展。ARM是一家在移动计算领域享有盛名的半导体公司，以设计高效能、低功耗的处理器著称，Cortex-A7 MPCore便是其产品线中的一员。 文档的标签也是"Cortex-A7 MPCore 技术参考手册"，这说明文档的关键词和焦点是围绕Cortex-A7 MPCore这一处理器，它可能包含处理器的技术细节、架构特点、编程接口以及性能参数等。 由于文档的内容部分截取显示了版权信息和版权声明，我们可以从中得知文档的版权声明（Copyright©2011-2013ARM.All rights reserved.）以及发行记录（如首次发布日期、版本号等）。另外，“ARMDDI0464F(ID051113)”可能是文档的一个标识代码。 文档中提到的“Copyright©2011-2013 ARM. All rights reserved.”这一段明确指出了版权信息，显示该文档及相关的处理器技术是由ARM公司所持有的，并受到法律保护，未经ARM公司的书面授权，任何部分都不得进行改编或复制。此外，文档中还提到了产品状态的网络地址（***），为读者提供了更多关于ARM产品和资源的访问途径。 在文档的保密性状态方面，它被标识为“Non-Confidential”，意味着文档内容不含有保密信息，可以公开分享，但同时文档也说明，使用文档中的任何信息，或者因任何信息错误或遗漏而造成的损失，或者产品使用不当，ARM公司不承担责任。此外，文档中也提及了在某些情况下使用、复制和披露文档的权利可能会受到ARM公司与接收文档的公司之间协议条款的限制。 “ProductStatusWebAddress ***”这部分表明该技术手册可能涉及的处理器产品已停产，因为提供的是一个较旧的网址，用于产品的状态查询。ARM作为一家不断进化的公司，其产品和技术随时间推移会不断更新迭代，所以提供的信息是针对某一成熟产品而言。 通过这份文档标题、描述、标签及部分内容，我们可以了解到与Cortex-A7 MPCore多核处理器相关的技术规范、版本更新、版权声明及产品状态等信息，这为开发者和工程师在设计和实现与Cortex-A7 MPCore相关的硬件与软件解决方案提供了基础支持。
资源推荐
资源详情
资源评论
Copyright © 2011-2013 ARM. All rights reserved.
ARM DDI 0464F (ID051113)
Cortex
™
-A7 MPCore
™
Revision: r0p5
Technical Reference Manual
Cortex-A7
ARM DDI 0464F Copyright © 2011-2013 ARM. All rights reserved. ii
ID051113 Non-Confidential
Cortex-A7 MPCore
Technical Reference Manual
Copyright © 2011-2013 ARM. All rights reserved.
Release Information
The following changes have been made to this book.
Proprietary Notice
Words and logos marked with
®
or
™
are registered trademarks or trademarks of ARM
®
in the EU and other countries,
except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the
trademarks of their respective owners.
Neither the whole nor any part of the information contained in, or the product described in, this document may be
adapted or reproduced in any material form except with the prior written permission of the copyright holder.
The product described in this document is subject to continuous developments and improvements. All particulars of the
product and its use contained in this document are given by ARM in good faith. However, all warranties implied or
expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.
This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or
damage arising from the use of any information in this document, or any error or omission in such information, or any
incorrect use of the product.
Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.
Confidentiality Status
This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license
restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this
document to.
Product Status
The information in this document is final, that is for a developed product.
Web Address
http://www.arm.com
Change history
Date Issue Confidentiality Change
03 October 2011 A Non-Confidential First release for r0p0
09 November 2011 B Non-Confidential First release for r0p1
11 January 2012 C Non-Confidential First release for r0p2
15 May 2012 D Non-Confidential First release for r0p3
19 November 2012 E Non-Confidential First release for r0p4
11 April 2013 F Non-Confidential First release for r0p5
ARM DDI 0464F Copyright © 2011-2013 ARM. All rights reserved. iii
ID051113 Non-Confidential
Contents
Cortex-A7 MPCore Technical Reference Manual
Preface
About this book .......................................................................................................... vii
Feedback .................................................................................................................... xi
Chapter 1 Introduction
1.1 About the Cortex-A7 MPCore processor ................................................................. 1-2
1.2 Compliance .............................................................................................................. 1-3
1.3 Features ................................................................................................................... 1-5
1.4 Interfaces ................................................................................................................. 1-6
1.5 Configurable options ................................................................................................ 1-7
1.6 Test features ............................................................................................................ 1-8
1.7 Product documentation and design flow .................................................................. 1-9
1.8 Product revisions ................................................................................................... 1-11
Chapter 2 Functional Description
2.1 About the Cortex-A7 MPCore processor functions .................................................. 2-2
2.2 Interfaces ................................................................................................................. 2-8
2.3 Clocking and resets ................................................................................................. 2-9
2.4 Power management ............................................................................................... 2-12
Chapter 3 Programmers Model
3.1 About the programmers model ................................................................................ 3-2
3.2 Execution environment support ............................................................................... 3-3
3.3 Advanced SIMD and VFP Extensions ..................................................................... 3-4
3.4 Security Extensions architecture ............................................................................. 3-5
3.5 Virtualization Extensions architecture ...................................................................... 3-7
3.6 Large Physical Address Extension architecture ...................................................... 3-8
3.7 Multiprocessing Extensions ..................................................................................... 3-9
3.8 Modes of operation ................................................................................................ 3-10
Contents
ARM DDI 0464F Copyright © 2011-2013 ARM. All rights reserved. iv
ID051113 Non-Confidential
3.9 Memory model ....................................................................................................... 3-11
Chapter 4 System Control
4.1 About system control ............................................................................................... 4-2
4.2 Register summary .................................................................................................... 4-3
4.3 Register descriptions ............................................................................................. 4-26
Chapter 5 Memory Management Unit
5.1 About the MMU ........................................................................................................ 5-2
5.2 Memory management system ................................................................................. 5-3
5.3 TLB organization ...................................................................................................... 5-5
5.4 TLB match process .................................................................................................. 5-6
5.5 Memory access sequence ....................................................................................... 5-7
5.6 MMU enabling and disabling ................................................................................... 5-8
5.7 External aborts ......................................................................................................... 5-9
5.8 MMU software accessible registers ....................................................................... 5-10
Chapter 6 L1 Memory System
6.1 About the L1 memory system .................................................................................. 6-2
6.2 Cache behavior ........................................................................................................ 6-3
6.3 L1 instruction memory system ................................................................................. 6-4
6.4 L1 data memory system .......................................................................................... 6-6
6.5 Data prefetching ...................................................................................................... 6-8
6.6 Direct access to internal memory ............................................................................ 6-9
Chapter 7 L2 Memory System
7.1 About the L2 Memory system .................................................................................. 7-2
7.2 Snoop Control Unit .................................................................................................. 7-3
7.3 Master interface ....................................................................................................... 7-5
7.4 Optional integrated L2 cache ................................................................................. 7-10
7.5 AXI privilege information ........................................................................................ 7-11
Chapter 8 Generic Interrupt Controller
8.1 About the GIC .......................................................................................................... 8-2
8.2 GIC functional description ........................................................................................ 8-3
8.3 GIC programmers model ......................................................................................... 8-6
Chapter 9 Generic Timer
9.1 About the Generic Timer .......................................................................................... 9-2
9.2 Generic timer functional description ........................................................................ 9-3
9.3 Timer programmers model ...................................................................................... 9-4
Chapter 10 Debug
10.1 About debug .......................................................................................................... 10-2
10.2 Debug register interfaces ....................................................................................... 10-4
10.3 Debug register summary ....................................................................................... 10-5
10.4 Debug register descriptions ................................................................................... 10-9
10.5 Debug events ....................................................................................................... 10-33
10.6 External debug interface ...................................................................................... 10-34
Chapter 11 Performance Monitoring Unit
11.1 About the Performance Monitoring Unit ................................................................. 11-2
11.2 PMU functional description .................................................................................... 11-3
11.3 PMU registers summary ........................................................................................ 11-4
11.4 PMU register descriptions ...................................................................................... 11-7
11.5 Events .................................................................................................................. 11-10
11.6 Interrupts .............................................................................................................. 11-12
11.7 Exporting PMU events ......................................................................................... 11-13
Contents
ARM DDI 0464F Copyright © 2011-2013 ARM. All rights reserved. v
ID051113 Non-Confidential
Appendix A Signal Descriptions
A.1 About the signal descriptions ................................................................................... A-2
A.2 Clock and reset signals ............................................................................................ A-3
A.3 Configuration signals ............................................................................................... A-4
A.4 Generic Interrupt Controller signals ......................................................................... A-5
A.5 Generic timer signals ............................................................................................... A-6
A.6 Power control signals ............................................................................................... A-7
A.7 ACE master interface signals .................................................................................. A-8
A.8 External debug interface ........................................................................................ A-13
A.9 DFT and MBIST interface signals .......................................................................... A-17
Appendix B Revisions
剩余268页未读，继续阅读
资源评论
_JMC
- 粉丝: 13
- 资源: 8
上传资源 快速赚钱
我的内容管理
展开
- 我的资源
快来上传第一个资源
我的收益 登录查看自己的收益
我的积分
登录查看自己的积分
我的C币
登录后查看C币余额
我的收藏 
我的下载 
下载帮助
前往需求广场，查看用户热搜最新资源
资源上传下载、课程学习等过程中有任何疑问或建议，欢迎提出宝贵意见哦~我们会及时处理！
点击此处反馈
安全验证
文档复制为VIP权益，开通VIP直接复制
信息提交成功