entity BS is
generic (NCELLS: natural range 2 to 120 := 2); -- number of
boundary scan cells
port (TCK, TMS, TDI: in bit;
TDO: out bit;
BSRin: in bit_vector(1 to NCELLS);
BSRout: inout bit_vector(1 to NCELLS);
CellType: bit_vector(1 to NCELLS));
-- '0' for input cell, '1' for output cell
end BS;
architecture behavior of BS is
signal IR,IDR: bit_vector(1 to 3); -- instruction registers
signal BSR1,BSR2: bit_vector(1 to NCELLS); -- boundary scan cells
signal BYPASS: bit; -- bypass bit
type TAPstate is (TestLogicReset, RunTest_Idle,
SelectDRScan, CaptureDR, ShiftDR, Exit1DR, PauseDR, Exit2DR, UpdateDR,
SelectIRScan, CaptureIR, ShiftIR, Exit1IR, PauseIR, Exit2IR, UpdateIR);
signal St: TAPstate;
begin
process (TCK)
begin
if (TCK='1') then
-- TAP Controller State Machine
case St is
when TestLogicReset =>
if TMS='0' then St<=RunTest_Idle; else St<=TestLogicReset; end if;
when RunTest_Idle =>
if TMS='0' then St<=RunTest_Idle; else St<=SelectDRScan; end if;