+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; DM ; 44 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; ALU ; 67 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; ALUCtl ; 8 ; 0 ; 3 ; 0 ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; Regs ; 49 ; 0 ; 0 ; 0 ; 64 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; CtlPart ; 6 ; 0 ; 0 ; 0 ; 8 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; IM ; 33 ; 0 ; 32 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
MIPS.rar_MIPS_mips 流水线_mips指令_流水线 （187个子文件） 
_info 3KB _vmake 26B CPU.vpr.ammdb 224B CPU.root_partition.cmp.ammdb 180B CPU.v.bak 2KB CPU_run_msim_rtl_verilog.do.bak 764B DMemory.v.bak 626B Control.v.bak 503B IMemory.v.bak 424B RegFile.v.bak 408B CPU_run_msim_rtl_verilog.do.bak1 764B CPU_run_msim_rtl_verilog.do.bak10 764B CPU_run_msim_rtl_verilog.do.bak11 764B CPU_run_msim_rtl_verilog.do.bak2 764B CPU_run_msim_rtl_verilog.do.bak3 764B CPU_run_msim_rtl_verilog.do.bak4 764B CPU_run_msim_rtl_verilog.do.bak5 764B CPU_run_msim_rtl_verilog.do.bak6 764B CPU_run_msim_rtl_verilog.do.bak7 764B CPU_run_msim_rtl_verilog.do.bak8 764B CPU_run_msim_rtl_verilog.do.bak9 764B CPU.cmp.bpm 453B CPU.map.bpm 420B CPU.(6).cnf.cdb 704KB CPU.rtlv_sg.cdb 641KB CPU.pre_map.cdb 638KB CPU.(0).cnf.cdb 9KB CPU.(4).cnf.cdb 6KB CPU.(3).cnf.cdb 4KB CPU.rtlv_sg_swap.cdb 3KB CPU.(1).cnf.cdb 2KB CPU.cmp.cdb 2KB CPU.(2).cnf.cdb 2KB CPU.(5).cnf.cdb 1KB CPU.root_partition.cmp.cdb 1KB CPU.map.cdb 1KB CPU.sgdiff.cdb 943B CPU.map_bb.cdb 939B CPU.root_partition.map.cdb 889B CPU.root_partition.map.hbdb.cdb 620B CPU.root_partition.map.reg_db.cdb 191B _primary.dat 2KB _primary.dat 1KB _primary.dat 841B _primary.dat 830B _primary.dat 593B logic_util_heursitic.dat 572B _primary.dat 385B _primary.dat 353B CPU.db_info 137B CPU.db_info 137B _primary.dbs 2KB _primary.dbs 1KB _primary.dbs 1KB _primary.dbs 782B _primary.dbs 538B _primary.dbs 492B _primary.dbs 445B CPU.tiscmp.slow_1200mv_85c.ddb 120KB CPU.tiscmp.slow_1200mv_0c.ddb 120KB CPU.tiscmp.fast_1200mv_0c.ddb 119KB CPU.asm_labs.ddb 10KB CPU.tis_db_list.ddb 224B CPU.root_partition.cmp.dfp 33B CPU_run_msim_rtl_verilog.do 764B CPU.done 26B CPU.root_partition.map.dpi 1KB CPU.root_partition.map.hbdb.hb_info 46B CPU.pre_map.hdb 64KB CPU.rtlv.hdb 64KB CPU.(6).cnf.hdb 58KB CPU.root_partition.map.hdb 10KB CPU.sgdiff.hdb 10KB CPU.cmp.hdb 10KB CPU.map.hdb 9KB CPU.root_partition.cmp.hdb 9KB CPU.root_partition.map.hbdb.hdb 9KB CPU.map_bb.hdb 9KB CPU.(1).cnf.hdb 4KB CPU.(0).cnf.hdb 3KB CPU.(4).cnf.hdb 2KB CPU.(3).cnf.hdb 2KB CPU.(2).cnf.hdb 2KB CPU.(5).cnf.hdb 783B CPU.hier_info 1.26MB CPU.hif 736B CPU.stingray_io_sim_cache.99um_tt_1200mv_0c_slow.hsd 1.18MB CPU.stingray_io_sim_cache.99um_tt_1200mv_85c_slow.hsd 1.18MB CPU.stingray_io_sim_cache.99um_ff_1200mv_0c_fast.hsd 1.17MB
CPU.lpc.html 2KB CPU.cmp.idb 775B modelsim.ini 11KB CPU.ipinfo 160B CPU.jdi 246B CPU.jdi 135B CPU.root_partition.map.kpt 209B CPU.cmp_merge.kpt 207B CPU.map.kpt 204B CPU.root_partition.cmp.kpt 203B CPU.cmp.kpt 202B共 187 条
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