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Uart.rar （14个子文件）

Uart

__MpdDataBase.txt.bak 3.73MB

__MpdDataBase.txt 3.73MB

ipdialog.dtd 9KB

xps_uartlite_v1_02_a

hdl

vhdl

uartlite_tx.vhd 23KB

xps_uartlite.vhd 25KB

uartlite_rx.vhd 22KB

baudrate.vhd 8KB

uartlite_core.vhd 23KB

data

xps_uartlite_v2_1_0.mui 4KB

xps_uartlite_v2_1_0.pao 4KB

xps_uartlite_v2_1_0.mpd 9KB

xps_uartlite.ucf 4KB

doc

html

change_log.html 11KB

xps_uartlite.pdf 529KB

DS571 June 22, 2011 www.xilinx.com 1

Product Specification

Xilinx in the United States and other countries. All other trademarks are the property of their respective owners.

Introduction

The Xilinx® XPS Universal Asynchronous Receiver

Transmitter (UART) Lite Interface connects to the PLB

(Processor Local Bus) and provides the controller

interface for asynchronous serial data transfer. This soft

IP core is designed to interface with the PLBV46.

Features

• PLB interface is based on PLB v4.6 specification

• Supports 8-bit bus interfaces

• One transmit and one receive channel (full duplex)

• 16-character Transmit FIFO and 16-character

Receive FIFO

• Configurable number of data bits in a character

(5-8)

• Configurable parity bit (odd or even)

• Configurable baud rate

LogiCORE IP XPS UART Lite

(v1.02.a)

DS571 June 22, 2011

Product Specification

LogiCORE IP Facts Table

Core Specifics

Supported

Device Family

(1)

Virtex-5,

Virtex-4,

Spartan-3E, Automotive Spartan-3E, Spartan-3,

Automotive Spartan-3, Spartan-3A,

Spartan-3AN, Automotive Spartan-3A,

Spartan-3A DSP, Automotive Spartan-3A DSP

Supported User

Interfaces

PLB v46

Resources

Slices LUTs FFS Block RAMs

See Ta ble 9 , Ta ble 1 0 and Ta bl e 11

Provided with Core

Documentation

Product Specification

Design Files

VHDL

Example Design

Not Provided

Test Be n c h

Not Provided

Constraints File

N/A

Simulation

Model

N/A

Tested Design Tools

Design Entry

Tools

ISE 13.2 software

Simulation

Mentor Graphics ModelSim

(2)

Synthesis Tools

XST 13.2

Support

Provided by Xilinx @ www.xilinx.com/support

1. For a complete listing of supported devices, see

IDS Embedded Edition Derivative Device Support

for this core.

2. For the supported versions of the tool, see the ISE Design Suite

13: Release Notes Guide.

DS571 June 22, 2011 www.xilinx.com 2

Product Specification

LogiCORE IP XPS UART Lite (v1.02.a)

Functional Description

The XPS UART Lite performs parallel-to-serial conversion on characters received through PLB and

serial-to-parallel conversion on characters received from a serial peripheral.

The XPS UART Lite is capable of transmitting and receiving 8, 7, 6 or 5-bit characters, with 1-stop bit and odd, even

or no parity. The XPS UART Lite can transmit and receive independently.

The device can be configured and its status can be monitored via the internal register set. The XPS UART Lite

generates an interrupt when Receive FIFO becomes non-empty or when transmit FIFO becomes empty. This

interrupt can be masked by using an interrupt enable/disable signal.

The device contains a 16-bit programmable baud rate generator and independent 16-word Transmit and Receive

FIFOs. The FIFOs can be enabled or disabled through software control.

The XPS UART Lite modules are shown in the top-level block diagram in Figure 1.

The XPS UART Lite modules are described in the next sections:

PLB Interface Module: The PLB Interface Module provides the interface to the PLB and implements PLB protocol

logic. PLB Interface Module is a bidirectional interface between a user IP core and the PLB bus standard. To simplify

the process of attaching an XPS UART Lite to the PLB, the core makes use of a portable, pre-designed bus interface

called PLB Interface Module that takes care of the bus interface signals, bus protocols, and other interfaces.

UART Lite Register Module: The Register Module includes all memory-mapped registers (as shown in Figure 1).

It interfaces to the PLB through the PLB Interface Module. It consists of an 8-bit status register, an 8-bit control

Interface Module.

UART Control Module: The UART Control Module consists of an RX module, a TX module, a parameterized baud

rate generator (BRG), and a Control Unit. It incorporates the state machine for initialization and start and stop bit

control logic.

X-Ref Target - Figure 1

Figure 1: Block Diagram of XPS UART Lite

PLB

Interface

PLB

Interface

Module

Serial

Interface

UART Lite

Receive Data

FIFO

Transmit Data

FIFO

Status Register

(STAT_REG)

Control Register

(CTRL_REG)

BRG

Module

Control

Unit

Interrupt

UART Control Module

DS571 June 22, 2011 www.xilinx.com 3

Product Specification

LogiCORE IP XPS UART Lite (v1.02.a)

Interrupts

If interrupts are enabled, an interrupt is generated when one of these two conditions is true:

1. When the Receive FIFO goes from empty to not empty, such as when the first valid character is received in the

Receive FIFO

2. When the Transmit FIFO goes from not empty to empty, such as when the last character in the Transmit FIFO is

transmitted

XPS UART Lite I/O Signals

The XPS UART Lite I/O signals are listed and described in Table 1.

Tabl e 1: XPS UART Lite I/O Signal Description

Port Signal Name Interface I/O

Initial

State

Description

System Signals

P1 SPLB_Clk System I - PLB clock

P2 SPLB_Rst System I - PLB reset, active high

PLB Interface Signals

P3 PLB_ABus[0 : 31] PLB I -

PLB address bus

P4 PLB_PAValid PLB I -

PLB primary address valid

P5 PLB_masterID[0 :

C_SPLB_MID_WIDTH - 1]

PLB I -

PLB current master identifier

P6 PLB_RNW PLB I -

PLB read not write

P7 PLB_BE[0 : (C_SPLB_DWIDTH/8) -

PLB I -

PLB byte enables

P8 PLB_size[0 : 3] PLB I -

PLB size of requested transfer

P9 PLB_type[0 : 2] PLB I -

PLB transfer type

P10 PLB_wrDBus[0 :

C_SPLB_DWIDTH - 1]

PLB I -

PLB write data bus

Unused PLB Interface Signals

P11 PLB_UABus[0 : 31] PLB I - PLB upper address bits

P12 PLB_SAValid PLB I - PLB secondary address valid

P13 PLB_rdPrim PLB I - PLB secondary to primary read

request indicator

P14 PLB_wrPrim PLB I - PLB secondary to primary write

request indicator

P15 PLB_abort PLB I - PLB abort bus request

P16 PLB_busLock PLB I - PLB bus lock

P17 PLB_MSize[0 : 1] PLB I - PLB data bus width indicator

P18 PLB_lockErr PLB I - PLB lock error

P19 PLB_wrBurst PLB I - PLB burst write transfer

P20 PLB_rdBurst PLB I - PLB burst read transfer

DS571 June 22, 2011 www.xilinx.com 4

Product Specification

LogiCORE IP XPS UART Lite (v1.02.a)

P21 PLB_wrPendReq PLB I - PLB pending bus write request

P22 PLB_rdPendReq PLB I - PLB pending bus read request

P23 PLB_wrPendPri[0 : 1] PLB I - PLB pending write request priority

P24 PLB_rdPendPri[0 : 1] PLB I - PLB pending read request priority

P25 PLB_reqPri[0 : 1] PLB I - PLB current request priority

P26 PLB_TAttribute[0 : 15] PLB I - PLB transfer attribute

PLB Slave Interface Signals

P27 Sl_addrAck PLB O 0 Slave address acknowledge

P28 Sl_SSize[0 : 1] PLB O 0 Slave data bus size

P29 Sl_wait PLB O 0 Slave wait

P30 Sl_rearbitrate PLB O 0 Slave bus rearbitrate

P31 Sl_wrDAck PLB O 0 Slave write data acknowledge

P32 Sl_wrComp PLB O 0 Slave write transfer complete

P33 Sl_rdDBus[0 : C_SPLB_DWIDTH -

PLB O 0 Slave read data bus

P34 Sl_rdDAck PLB O 0 Slave read data acknowledge

P35 Sl_rdComp PLB O 0 Slave read transfer complete

P36 Sl_MBusy[0 :

C_SPLB_NUM_MASTERS - 1]

PLB O 0 Slave busy

P37 Sl_MWrErr[0 :

C_SPLB_NUM_MASTERS - 1]

PLB O 0 Slave write error

P38 Sl_MRdErr[0 :

C_SPLB_NUM_MASTERS - 1]

PLB O 0 Slave read error

Unused PLB Slave Interface Signals

P39 Sl_wrBTerm PLB O 0 Slave terminate write burst transfer

P40 Sl_rdWdAddr[0 : 3] PLB O 0 Slave read word address

P41 Sl_rdBTerm PLB O 0 Slave terminate read burst transfer

P42 Sl_MIRQ[0 :

C_SPLB_NUM_MASTERS - 1]

PLB O 0 Master interrupt request

UART Lite Interface Signals

P43 RX UART Lite I - Receive Data

P44 TX UART Lite O 0 Transmit Data

P45 Interrupt UART Lite O 0 UART Interrupt

Tabl e 1: XPS UART Lite I/O Signal Description (Cont’d)

Port Signal Name Interface I/O

Initial

State

Description

DS571 June 22, 2011 www.xilinx.com 5

Product Specification

LogiCORE IP XPS UART Lite (v1.02.a)

XPS UART Lite Design Parameters

To allow the user to obtain an XPS UART Lite that is uniquely tailored for the system, certain features can be

parameterized in the XPS UART Lite design. This allows the user to configure a design that utilizes the resources

required by the system only and that operates with the best possible performance. The features that can be

parameterized in the XPS UART Lite design are as shown in Table 2.

Tabl e 2: XPS UART Lite Design Parameters

Generic Feature/Description Parameter Name Allowable Values

Default

Value

VHDL Type

System Parameter

G1 Target FPGA family C_FAMILY spartan3e, aspartan3e,

spartan3,

aspartan3,

spartan3a, spartan3an,

aspartan3a,

spartan3adsp,

aspartan3adsp, virtex4,

qvirtex4, qrvirtex4, virtex5

virtex5 string

G2 System clock frequency (in

Hz) driving the UART Lite

peripheral

C_SPLB_CLK_

FREQ_HZ

integer (ex. 100000000) 100_

000_

000

Integer

PLB Parameters

G3 PLB Base Address C_BASEADDR Valid Address

(1)

None

(3)

std_logic_

vector

G4 PLB High Address C_HIGHADDR Valid Address

(2)

None

(3)

std_logic_

vector

G5 PLB least significant address

bus width

C_SPLB_AWIDTH 32 32 integer

G6 PLB data width C_SPLB_DWIDTH 32, 64, 128 32 integer

G7 Selects point-to-point or

shared bus topology

C_SPLB_P2P 0 = Shared Bus Topology

1 = Point-to-Point Bus

Topology

(4)

0 integer

G8 PLB Master ID Bus Width C_SPLB_MID_

WIDTH

log

(C_SPLB_NUM_

MASTERS) with a

minimum value of 1

1 integer

G9 Number of PLB Masters C_SPLB_NUM_

MASTERS

1 - 16 1 integer

G10 Support Bursts C_SPLB_SUPPORT_

BURSTS

0 0 integer

G11 Width of the Slave Data Bus C_SPLB_NATIVE_

DWIDTH

32 32 integer

UART Lite Parameters

G12 Baud rate of the UART Lite in

bits per second

C_BAUDRATE integer (ex. 128000) 128_

000

<RD

Red>[5]

Integer

G13 The number of data bits in

the serial frame

C_DATA_BITS 5 - 8 8 Integer

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