of-reconfig-notifier-error-inject.rar_K.

/* * drx3973d_map_firm.h * * Copyright (C) 2006-2007 Micronas * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * version 2 only, as published by the Free Software Foundation. * * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA * 02110-1301, USA * Or, point your browser to http://www.gnu.org/copyleft/gpl.html */ #ifndef __DRX3973D_MAP__H__ #define __DRX3973D_MAP__H__ /* * Note: originally, this file contained 12000+ lines of data * Probably a few lines for every firwmare assembler instruction. However, * only a few defines were actually used. So, removed all uneeded lines. * If ever needed, the other lines can be easily obtained via git history. */ #define HI_COMM_EXEC__A 0x400000 #define HI_COMM_MB__A 0x400002 #define HI_CT_REG_COMM_STATE__A 0x410001 #define HI_RA_RAM_SRV_RES__A 0x420031 #define HI_RA_RAM_SRV_CMD__A 0x420032 #define HI_RA_RAM_SRV_CMD_RESET 0x2 #define HI_RA_RAM_SRV_CMD_CONFIG 0x3 #define HI_RA_RAM_SRV_CMD_EXECUTE 0x6 #define HI_RA_RAM_SRV_RST_KEY__A 0x420033 #define HI_RA_RAM_SRV_RST_KEY_ACT 0x3973 #define HI_RA_RAM_SRV_CFG_KEY__A 0x420033 #define HI_RA_RAM_SRV_CFG_DIV__A 0x420034 #define HI_RA_RAM_SRV_CFG_BDL__A 0x420035 #define HI_RA_RAM_SRV_CFG_WUP__A 0x420036 #define HI_RA_RAM_SRV_CFG_ACT__A 0x420037 #define HI_RA_RAM_SRV_CFG_ACT_SLV0_ON 0x1 #define HI_RA_RAM_SRV_CFG_ACT_BRD__M 0x4 #define HI_RA_RAM_SRV_CFG_ACT_BRD_OFF 0x0 #define HI_RA_RAM_SRV_CFG_ACT_BRD_ON 0x4 #define HI_RA_RAM_SRV_CFG_ACT_PWD_EXE 0x8 #define HI_RA_RAM_USR_BEGIN__A 0x420040 #define HI_IF_RAM_TRP_BPT0__AX 0x430000 #define HI_IF_RAM_USR_BEGIN__A 0x430200 #define SC_COMM_EXEC__A 0x800000 #define SC_COMM_EXEC_CTL_STOP 0x0 #define SC_COMM_STATE__A 0x800001 #define SC_RA_RAM_PARAM0__A 0x820040 #define SC_RA_RAM_PARAM1__A 0x820041 #define SC_RA_RAM_CMD_ADDR__A 0x820042 #define SC_RA_RAM_CMD__A 0x820043 #define SC_RA_RAM_CMD_PROC_START 0x1 #define SC_RA_RAM_CMD_SET_PREF_PARAM 0x3 #define SC_RA_RAM_CMD_GET_OP_PARAM 0x5 #define SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1 #define SC_RA_RAM_LOCKTRACK_MIN 0x1 #define SC_RA_RAM_OP_PARAM_MODE_2K 0x0 #define SC_RA_RAM_OP_PARAM_MODE_8K 0x1 #define SC_RA_RAM_OP_PARAM_GUARD_32 0x0 #define SC_RA_RAM_OP_PARAM_GUARD_16 0x4 #define SC_RA_RAM_OP_PARAM_GUARD_8 0x8 #define SC_RA_RAM_OP_PARAM_GUARD_4 0xC #define SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0 #define SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10 #define SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20 #define SC_RA_RAM_OP_PARAM_HIER_NO 0x0 #define SC_RA_RAM_OP_PARAM_HIER_A1 0x40 #define SC_RA_RAM_OP_PARAM_HIER_A2 0x80 #define SC_RA_RAM_OP_PARAM_HIER_A4 0xC0 #define SC_RA_RAM_OP_PARAM_RATE_1_2 0x0 #define SC_RA_RAM_OP_PARAM_RATE_2_3 0x200 #define SC_RA_RAM_OP_PARAM_RATE_3_4 0x400 #define SC_RA_RAM_OP_PARAM_RATE_5_6 0x600 #define SC_RA_RAM_OP_PARAM_RATE_7_8 0x800 #define SC_RA_RAM_OP_PARAM_PRIO_HI 0x0 #define SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000 #define SC_RA_RAM_OP_AUTO_MODE__M 0x1 #define SC_RA_RAM_OP_AUTO_GUARD__M 0x2 #define SC_RA_RAM_OP_AUTO_CONST__M 0x4 #define SC_RA_RAM_OP_AUTO_HIER__M 0x8 #define SC_RA_RAM_OP_AUTO_RATE__M 0x10 #define SC_RA_RAM_LOCK__A 0x82004B #define SC_RA_RAM_LOCK_DEMOD__M 0x1 #define SC_RA_RAM_LOCK_FEC__M 0x2 #define SC_RA_RAM_LOCK_MPEG__M 0x4 #define SC_RA_RAM_BE_OPT_ENA__A 0x82004C #define SC_RA_RAM_BE_OPT_ENA_CP_OPT 0x1 #define SC_RA_RAM_BE_OPT_DELAY__A 0x82004D #define SC_RA_RAM_CONFIG__A 0x820050 #define SC_RA_RAM_CONFIG_FR_ENABLE__M 0x4 #define SC_RA_RAM_CONFIG_FREQSCAN__M 0x10 #define SC_RA_RAM_CONFIG_SLAVE__M 0x20 #define SC_RA_RAM_IF_SAVE__AX 0x82008E #define SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x8200D1 #define SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE 0x9 #define SC_RA_RAM_IR_COARSE_2K_FREQINC__A 0x8200D2 #define SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE 0x4 #define SC_RA_RAM_IR_COARSE_2K_KAISINC__A 0x8200D3 #define SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE 0x100 #define SC_RA_RAM_IR_COARSE_8K_LENGTH__A 0x8200D4 #define SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE 0x8 #define SC_RA_RAM_IR_COARSE_8K_FREQINC__A 0x8200D5 #define SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE 0x8 #define SC_RA_RAM_IR_COARSE_8K_KAISINC__A 0x8200D6 #define SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE 0x200 #define SC_RA_RAM_IR_FINE_2K_LENGTH__A 0x8200D7 #define SC_RA_RAM_IR_FINE_2K_LENGTH__PRE 0x9 #define SC_RA_RAM_IR_FINE_2K_FREQINC__A 0x8200D8 #define SC_RA_RAM_IR_FINE_2K_FREQINC__PRE 0x4 #define SC_RA_RAM_IR_FINE_2K_KAISINC__A 0x8200D9 #define SC_RA_RAM_IR_FINE_2K_KAISINC__PRE 0x100 #define SC_RA_RAM_IR_FINE_8K_LENGTH__A 0x8200DA