7 Series FPGAs
Configuration
User Guide
UG470 (v1.7) October 22, 2013
7 Series FPGAs Configuration User Guide www.xilinx.com UG470 (v1.7) October 22, 2013
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Revision History
The following table shows the revision history for this document.
Date Version Revision
03/01/2011 1.0 Initial Xilinx release.
03/28/2011 1.1 Changed name of “New Features” section to 7 Series FPGA Features, added note to first
bullet, and added last sentence to fourth bullet. Revised Design Considerations section
for clarity: Added Configuration Bitstream Lengths section and Table 1-1. Added
Configuration Pins section and Table 2-2, Table 2-3, and Table 2-4. Moved Configuration
Banks Voltage Select section from Chapter 1 to Chapter 2 and added Table 2-6. Added
signal CFGBVS to Figure 2-2, Figure 2-5, Figure 2-10, Figure 2-14 and Figure 2-17.
UG470 (v1.7) October 22, 2013 www.xilinx.com 7 Series FPGAs Configuration User Guide
10/26/2011 1.2 Chapter 1, Configuration Overview:
• Changed VCC_CONFIG to VCCO_0
• Added Virtex-7 family to Table 1-1
•Added Stacked Silicon Interconnect section
Chapter 2, Configuration Interfaces:
• Corrected pin names
D[04-07] and D[08-15] in Table 2-2
• Added a Note in Table 2-4 describing the function of the DONE pin
• Added cross-reference to the DONE pin in Table 2-4 to the following: Table 2-7,
Figure 2-2 note 2, Table 2-8, Figure 2-5 note 3, Table 2-12, Figure 2-10 note 1,
Table 2-15, Figure 2-14 note 8, Figure 2-17 note 8
• Revised the title of Figure 2-15
• Updated the families that Master BPI synchronous read mode supports in the first
sentence of the second paragraph in Synchronous Read Mode Support
• Expanded the description of the BitGen -g BPI_sync_mode option in Synchronous
Read Mode Support
• Clarified the BitGen ConfigRate setting and revised the CCLK frequency in the first
paragraph of, and revised the ADDR range bullet in Determining the Maximum
Configuration Clock Frequency
Chapter 5, Configuration Details:
• Changed VCC_CONFIG to VCCO_0
• Clarified the BPI asynchronous and synchronous read modes
• Revised the function description of the DONE pin in Startup (Step 8) and added cross-
reference to the DONE pin in Table 2-4
• Updated the support for the BitGen DriveDone option in Table 5-12 note 2
• Clarified the description of the JTAG instruction register in JTAG Instructions
• Clarified the description of WRAP_ERROR_1 and WRAP_ERROR_0 in Table 5-36
Chapter 8, Readback CRC:
• Corrected names of clock source primitives ICAPE2 and STARTUPE2 in Table 8-1
02/03/2012 1.3 Revised Table 1-1. Added Init_B, DONE, and CCLK pin names to Master SPI x4 column
in Table 2-2. Added URL link to iMPACT Help documentation in Master SPI
Configuration Mode. Added Determining the Maximum Configuration Clock
Frequency. Added Table 5-15.
Date Version Revision
7 Series FPGAs Configuration User Guide www.xilinx.com UG470 (v1.7) October 22, 2013
07/19/2012 1.4 Changed “ICAP” to “ICAPE2” throughout document. CFGBVS descriptions updated
throughout document. Changed “4.7Ω“ pull-up/pull-down resistor value to “1 kΩ or
greater” under Overview. Changed “7 Series Features” heading to 7 Series FPGAs
Configuration Differences from Previous FPGA Generations. Under this heading
changed “D00” in note to “D0”, clarified the fourth bullet, added the sixth and seventh
bullets, clarified the eighth bullet, and added the last paragraph. Replaced Table 1-1.
Clarified the second paragraph under Protecting the FPGA Bitstream against
Unauthorized Duplication by removing the word “unique”. Added the last sentence
under Loading Multiple FPGAs with the Same Configuration Bitstream. Clarified first
two paragraphs under Stacked Silicon Interconnect. Clarified the descriptions of
CFGBVS, TDO, PROGRAM_B, CCLK, PUDC_B, CSO_B, and DOUT in Table 2-4.
Clarified Configuration Banks Voltage Select section and Table 2-5 and Table 2-6.
Clarified description of PUDC_B in Table 2-7, Table 2-8, Table 2-12, and Table 2-15.
Added “RS[1:0]” to Figure 2-4. Changed references from XAPP974 to XAPP586 and
XAPP502 to XAPP583. Added last sentence to second paragraph and changed “flash
timing” to “x1 mode sequence” under Master SPI Configuration Mode. Added note
relevant to Figure 2-11. Added last paragraph under SPI Densities over 128 Mb. Added
fourth and fifth paragraphs under Synchronous Read Mode Support. Added last
paragraph under Configuring through Boundary-Scan. Added V
CCBRAM
to first and last
paragraphs, deleted last paragraph under Device Power-Up (Step 1). Modified
Figure 5-4. Clarified definition of GWE in Table 5-12 and added table note 3. Changed
“PROG” to PROGRAM_B” under Loading Encrypted Bitstreams. Clarified first
paragraph under Bitstream Encryption and Internal Configuration Access Port
(ICAPE2). Clarified bit position descriptions in Table 5-15 and associated text under
eFUSE Control Register (FUSE_CNTL). Changed “7 Series FPGA Unique Device
Identifier (Device DNA)” heading to Device Identifier (Device DNA), clarified first
paragraph, and added second paragraph. Added the last two sentences to first
paragraph under JTAG Access to Device Identifier. Clarified first paragraph and added
fifth paragraph in Chapter 6, Readback and Configuration Verification. Added SPI 32-bit
addressing mode support exception under Fallback MultiBoot. Changed “PROG” to
PROGRAM_B” in first paragraph under IPROG. Updated address bits in Figure 7-3.
11/02/2012 1.5 Deleted XC7A350T, XC7V1500T, and XC7VH290T devices from Table 1-1. Changed
configuration bitstream length (bits) for XC7VH580T and XC7VH870T devices in
Table 1-1. Corrected bit value for RBCRC_EN in Table 5-30. Deleted Reset On Error,
which is automatically enabled with the fallback feature, in Chapter 7, Reconfiguration
and MultiBoot. Updated description for DIN and D[00-31] pins in Table 2-4. Deleted
following tables: 7 Series FPGA Serial Configuration Interface Pins, 7 Series FPGA
SelectMAP Configuration Interface Pins, 7 Series FPGA SPI Configuration Interface Pins,
and 7 Series FPGA Master BPI Configuration Interface Pins. Updated paragraph five in
Synchronous Read Mode Support. Updated bullets in Golden Image and MultiBoot
Image Design Requirements and Initial MultiBoot Design Considerations
01/02/2013 1.6 Added reference to Vivado Design Suite (added last paragraph and note under 7 Series
FPGAs Configuration Differences from Previous FPGA Generations). Simplified part
numbers in Table 1-1. Corrected XC7V2000T device JTAG IDCODE (added Note 2 to
Table 1-1). Changed cell heading in Table 5-1 from “Xilinx Software Tool” to “Xilinx
Tool”. Highlighted limitation imposed by a specific eFUSE security option (added
caution to first row in Table 5-15 and replaced second-to-last paragraph of eFUSE
Control Register (FUSE_CNTL) with a caution).
10/22/2013 1.7 Added 7A35T, 7A50T, and 7A75T devices. Updated CFGBVS descriptions throughout
document (CFGBVS determines supported I/O voltages in Banks 14 and 15 in Artix-7
and Kintex-7 devices). Removed references to fallback not being supported in SPI 32-bit
addressing mode.
Date Version Revision
7 Series FPGAs Configuration User Guide www.xilinx.com 5
UG470 (v1.7) October 22, 2013
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Preface: About This Guide
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Additional Support Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chapter 1: Configuration Overview
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7 Series FPGAs Configuration Differences from Previous FPGA Generations 12
Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Configuration Bitstream Lengths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
FPGA Configuration Data Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Master Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Slave Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
JTAG Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
The Basic Configuration Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
The Low-Cost Configuration Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
The High-Speed Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Protecting the FPGA Bitstream against Unauthorized Duplication. . . . . . . . . . . . . . . 17
Loading Multiple FPGAs with the Same Configuration Bitstream . . . . . . . . . . . . . . . 17
Configuration Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Stacked Silicon Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Chapter 2: Configuration Interfaces
Configuration Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Configuration Banks Voltage Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Serial Configuration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Slave Serial Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Master Serial Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Clocking Serial Configuration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
SelectMAP Configuration Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Single Device SelectMAP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Microprocessor-Driven SelectMAP Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
SelectMAP Data Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
CSI_B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
RDWR_B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
CCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Continuous SelectMAP Data Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Non-Continuous SelectMAP Data Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
SelectMAP Data Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Master SPI Configuration Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Master SPI Dual (x2) and Quad (x4) Read Commands . . . . . . . . . . . . . . . . . . . . . . . . . 46
SPI Densities over 128 Mb. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
SPI Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table of Contents
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