`timescale 1ns/1ns
//////////////////////////////////////////
// Company: UESTC
// Engineer: Zhang Peng
// Create Date: 09/21/2008
// Design Name:
// Module Name: qpsk
// Project Name:
// Target Devices:
// Tool versions: ModelSim 6.0
// Description:
// Additional Comments:
///////////////////////////////////////////
module qpsk(clk, rst, x, y);
input clk;
input rst;
input x;
output y;
reg [2:0] count;
reg [1:0] xreg,yreg;
reg [3:0] carriers;
//reg [1:0] yy;
always @(posedge clk or negedge rst)
begin
if(!rst)
count <= 3'b000;
else
count <= count +1;
end
always @(posedge clk or negedge rst)
begin
if(!rst)
xreg <= 2'b00;
else
if(count[1:0]==2'b11)
xreg <= {xreg[0], x};
else
xreg <= xreg;
end
always @(posedge clk or negedge rst)
begin
if(!rst)
begin
carriers <= 4'b000;
yreg <= 2'b00;
end
else
begin
case(count)
3'b000:
begin
yreg <= xreg;
carriers <= 4'b1100;
end
3'b010: carriers <= 4'b1001;
3'b100: carriers <= 4'b0011;
3'b110: carriers <= 4'b0110;
default: carriers <= carriers;
endcase
end
end
assign y = (yreg == 2'b00) ? carriers[3] :
(yreg == 2'b01) ? carriers[2] :
(yreg == 2'b10) ? carriers[1] :
(yreg == 2'b11) ? carriers[0] : 0;
endmodule
`timescale 1ns/1ns
//////////////////////////////////////////
// Company: UESTC
// Engineer: Zhang Peng
// Create Date: 09/21/2008
// Design Name:
// Module Name: qpsk_de
// Project Name:
// Target Devices:
// Tool versions: ModelSim 6.0
// Description:
// Additional Comments:
///////////////////////////////////////////
module qpsk_de(clk, rst, x, y);
input clk;
input rst;
input x;
output y;
reg [7:0] temp;
reg [7:0] temp2;
reg [2:0] count;
wire [1:0] y1;
always @(posedge clk or negedge rst)
begin
if (!rst)
begin
count <= 3'b111;
temp <= 8'b0;
temp2 <= 8'b0;
end
else
begin
temp2 <= {temp2[6:0], x};
count <= count +1;
if (count == 3'b111)
temp <= temp2;
else
temp <= temp;
end
end
assign y1 = (rst == 0) ? 2'b00 :
(temp == 8'b11110000) ? 2'b00 :
(temp == 8'b11000011) ? 2'b01 :
(temp == 8'b00001111) ? 2'b10 :
(temp == 8'b00111100) ? 2'b11 : 2'b00;
assign y = (count[2] == 0) ? y1[1] : y1[0];
endmodule
