Technical Committee
Utopia Level 2, Version 1.0
af-phy-0039.000
June 1995
Level 2, Version 1.0 Utopia, An ATM-PHY Interface Specification
Page ii ATM Forum Technical Committee
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Utopia, An ATM-PHY Interface Specification Level 2, Version 0.95
ATM Forum Technical Committee Page iii
TABLE OF CONTENTS
1. INTRODUCTION 1
1.1. Document Purpose and Background 1
1.2. Scope 1
1.3. Statement of Compatibility with Level 1 Document 2
1.4. Document Contents 2
2. FUNCTIONAL DESCRIPTION 3
2.1 Conventions 3
2.2. Terminology related to Utopia Scope 3
2.3. Other Terminology 5
2.3. Reference Model and Configurations 5
2.4. Interface Rates 7
2.5. Device Capabilities 7
2.6. Cell Processing 7
3. AMENDED LEVEL 1 SPECIFICATION 8
3.1. Introduction and Motivation 8
3.2. Level 1 Section 4.2 on Transmit Operation 8
3.3. Level 1 Section 5.2 on Receive Operation 12
4. MPHY DATA PATH OPERATION 16
4.1. Signals 16
4.2. Operation with 1 TxClav & 1 RxClav Signal 18
4.3 Direct status indication 25
4.4 Multiplexed status polling 30
5. TIMING DETAILS AT 25, 33 AND 50 MHZ 35
5.1 A.C. characteristics 35
5.2 D.C. characteristics 45
5.3 Signals TxRef* and RxRef* 47
6. DATA PATH SIGNAL SUMMARY 48
6.1. Transmit Interface Signals 48
6.2. Receive Interface Signals 48
APPENDIX 1. METHOD TO SUPPORT A LARGER NUMBER OF PHYS 49
A1.1. Example 49
A1.2 Special cases 50
A2.3 Impact on the PHY Layer 50
A2.4 Impact on the ATM Layer 50
APPENDIX 2. MANAGEMENT INTERFACE 51
A2.1 Scope 51
A2.2 Introduction 51
A2.3 Serial interface 51
A2.4 Parallel interface 60
A2.5 D.C. characteristics 64
A2.6 Notes 65
APPENDIX 3. REFERENCES 66
Utopia, An ATM-PHY Interface Specification Level 2, Version 1.0
ATM Forum Technical Committee Page 1
1. Introduction
1.1. Document Purpose and Background
This document describes a number of enhancements to the Universal Test & Operations PHY
Interface for ATM (UTOPIA) data path interface [1]. This document assumes familiarity with
the Level 1 Utopia document [1], which specifies the following :
1. an 8-bit wide data path, using an octet-level handshake, operating up to 25 MHz, with a
single PHY device
2. an 8-bit wide data path, using an cell-level handshake, operating up to 25 MHz, with a
single PHY device
3. a cell format and extra signals for a 16-bit wide data path for future use
The Level 1 Specification was designed to deal with the following PHY layer interfaces :
1. 155.52 Mbps (SONET/OC-3c)
2. 155.52 Mbps (8B/10B block coded)
3. 100 Mbps (4B/5B TAXI)
4. 44.1236 Mbps (DS-3)
5. 51.84 Mbps (OC-1)
We recommend use of this document in conjunction with the Level 1 Specification, since only
updates and changes to it are described here.
1.2. Scope
Various levels of the Utopia specification will document enhancements to the Level 1
specification. Level 2, described in this document addresses the following areas :
1.2.1. Definition of AC and DC Characteristics
The description on AC characteristics features three different clock rates :
a) 25 MHz : Better definition of the timing at this speed.
b) 33 MHz data path interface operation, intended to simplify PCI Bus ATM layer designs. This
clock rate is used both with 8 and 16-bit wide data paths. The 16-bit wide data path uses the
cell format and signals described in the Level 1 document.
c) 50 MHz data path interface operation, intended for a 16-bit interface at line rates of 622 Mbps.
1.2.2. Multi-PHY (MPHY) Operation
This will define the "physical" operation of up to n PHY devices where,
n =< 8 at ATM layers intended for 155 Mbps;
n =< 4 at ATM layers intended for 622 Mbps.
with the virtual space set up for n =< 31.
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