APPENDIX
B
1
1. VHDL Basics
1.1. Valid Names
1.2. Comments
1.3. Entity and Architecture
1.4. Ports
1.5. Signals and Variables
1.6. Type
1.6.1. STD_LOGIC
1.6.2. Enumerated Type
1.7. Libraries and Packages
VHDL Language Reference
A valid name in VHDL consists of a letter followed by any number of letters or
numbers, without spaces. VHDL is not case sensitive. An underscore may be used
within a name, but may not begin or end the name. Two consecutive underscores are
not permitted.
1.1 VALID NAMES
EXAMPLES
Valid names:
decode4
just_in_time
What_4
Invalid names:
4decode (begins with a digit)
in__time (two consecutive underscores)
_What_4 (begins with underscore)
my design (space inside name)
your_words? (special character ? not allowed)
A comment is explanatory text that is ignored by the VHDL compiler. It is indi-
cated by two consecutive hyphens.
1.2 COMMENTS
EXAMPLE
-- This is a comment.