'timescale 1ns/100ps
module DPram (CLK,Q,Data,Write,Read,WAddr,RAddr);
parameter Width=8;
parameter Depth=8;
parameter addr=3;
input Write,Read;
input CLK;
input [Addr-1:0] WAddr,[Addr-1:0] RAddr;
input [Width-1:0] D;
output [Width-1:0] Q;
reg [Width-1:0] Q;
reg [Width-1:0] mem [Depth-1:0];
always @(posedge CLK) // the write part
begin
if(Write)
mem[WAddr]<= #1 Data;
end
always @(posedge CLK) // the read part
begin
if(Read)
Q<= #1 mem[RAddr];
end
endmodule
'timescale 1ns/100ps
module DPram_t;
parameter width=8; // bus width
parameter addr=3; //of address lines
parameter depth=20; // number of vectors
parameter half_period=100; //100ns period
reg clk,write,read,rst; //addition rst
reg [addr-1:0] waddr,raddr;
reg [width-1:0] data_in [depth-1:0];
reg [width-1:0] data_out [depth-1:0];
reg [width-1:0] data,q;
integer i,j,k,numerrors;
DPram m ( .Data(data),.Q(q),.CLK(clk),
.Write(write),.Read(read),
.WAddr(waddr),.RAddr(raddr)
);
initial // dates to be read and writed
begin
data_in[0]=8'h00; data_out[0]=8'hxx;
data_in[1]=8'h01; data_out[1]=8'hxx;
data_in[2]=8'h02; data_out[2]=8'hxx;
data_in[3]=8'h04; data_out[3]=8'hxx;
data_in[4]=8'h08; data_out[4]=8'hxx;
data_in[5]=8'h10; data_out[5]=8'hxx;
data_in[6]=8'h20; data_out[6]=8'hxx;
data_in[7]=8'h40; data_out[7]=8'hxx;
data_in[8]=8'h80; data_out[8]=8'hxx;
data_in[9]=8'h07; data_out[9]=8'h01;
data_in[10]=8'h08; data_out[10]=8'h02;
data_in[11]=8'h09; data_out[11]=8'h04;
data_in[12]=8'h10; data_out[12]=8'h08;
data_in[13]=8'h11; data_out[13]=8'h10;
data_in[14]=8'h12; data_out[14]=8'h20;
data_in[15]=8'h13; data_out[15]=8'h40;
data_in[16]=8'h14; data_out[16]=8'h80;
data_in[17]=8'haa; data_out[17]=8'h80;
data_in[18]=8'h55; data_out[18]=8'haa;
data_in[19]=8'haa; data_out[19]=8'h55;
end
initial
begin
rst=0;
clk=0;
write=0;
read=0;
waddr=0;
radder=0;
data=0;
numerrors=0;
# 200 rst=1; //200ns later,rst reset to DPram
# 200 rst=0;
end
always # half_period clk=~clk;
initial
begin
#2450 write=1;
#8000 write=0;
read=1;
#8000 read=0;
write=1;
#1000 read=1;
end
initial
begin
#1450 for(k=0;k<=width-1;k=k+1)
#1000 waddr=k;
waddr=0;
end
initial
begin
#9450;
for(j=0;j<=width-1;j=j+1)
#1000 raddr=j;
raddr=0;
end
initial
begin
for(i=1;i<=depth-1;i=i+1)
begin@(negedge clk)
data=data_in;
q=data_out;
end
end
endmodule