dpram.rar_DPRAM CPLD_dpram_dpram vhdl_idt70V05 VERILOG_verilog

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity dpram2 is port ( -- reset: in std_logic; wr1: in std_logic; wr2: in std_logic; rd1: in std_logic; rd2: in std_logic; cs1: in std_logic; cs2: in std_logic; clk: in std_logic; data1_in: in std_logic_vector(7 downto 0); data2_in: in std_logic_vector(7 downto 0); data1_out: out std_logic_vector(7 downto 0); data2_out: out std_logic_vector(7 downto 0); addr1: in std_logic_vector(4 downto 0); addr2: in std_logic_vector(4 downto 0) ); end dpram2; architecture behavioral of dpram2 is constant size : integer :=31; type ram_array is array ( integer range <> ) of std_logic_vector(7 downto 0); signal ram : ram_array(0 to size); begin process (clk) variable state: integer range 0 to 24; variable addr1_i: integer range 0 to size; variable addr2_i: integer range 0 to size; variable wr1_ack: std_logic; variable wr2_ack: std_logic; variable rd1_ack: std_logic; variable rd2_ack: std_logic; begin --if(reset='1') then -- state :=0 ; --addr1_i :=0; --addr2_i :=0; --data1 <= "00000000"; --data2 <= "00000000"; if (clk'event and clk = '1') then if((cs1 = '0') and (cs2='0')) then state := 0 ; end if; if((cs1='1') and (rd1='1') and (cs2='0')) then wr1_ack :='0'; wr2_ack :='0'; rd2_ack :='0'; if (rd1_ack ='0') then state :=1 ; else state :=2 ; end if; end if; if((cs2='1') and (rd2='1') and (cs1='0')) then wr1_ack :='0'; wr2_ack :='0'; rd1_ack :='0'; if (rd2_ack ='0') then state :=3 ; else state :=4 ; end if; end if; if((cs1='1') and (wr1='1') and (cs2='0')) then rd1_ack :='0'; wr2_ack :='0'; rd2_ack :='0'; if (wr1_ack ='0') then state :=5 ; else state :=6 ; end if; end if; if((cs2='1') and (wr2='1') and (cs1='0')) then rd1_ack :='0'; wr1_ack :='0'; rd2_ack :='0'; if (wr2_ack ='0') then state :=7 ; else state :=8 ; end if; end if; if((cs1='1') and (rd1='1') and (cs2='1') and (rd2='1')) then wr1_ack :='0'; wr2_ack :='0'; if (rd1_ack='0' and rd2_ack='0') then state :=9; end if; if (rd1_ack='0' and rd2_ack='1') then state :=10; end if; if (rd1_ack='1' and rd2_ack='0') then state :=11; end if; if (rd1_ack='1' and rd2_ack='1') then state :=12; end if; end if; if((cs1='1') and (rd1='1') and (cs2='1') and (wr2='1')) then wr1_ack :='0'; rd2_ack :='0'; if (rd1_ack='0' and wr2_ack='0') then state :=13; end if; if (rd1_ack='0' and wr2_ack='1') then state :=14; end if; if (rd1_ack='1' and wr2_ack='0') then state :=15; end if; if (rd1_ack='1' and wr2_ack='1') then state :=16; end if; end if; if((cs1='1') and (wr1='1') and (cs2='1') and (rd2='1')) then rd1_ack :='0'; wr2_ack :='0'; if (wr1_ack='0' and rd2_ack='0') then state :=17; end if; if (wr1_ack='0' and rd2_ack='1') then state :=18; end if; if (wr1_ack='1' and rd2_ack='0') then state :=19; end if; if (wr1_ack='1' and rd2_ack='1') then state :=20; end if; end if; if((cs1='1') and (wr1='1') and (cs2='1') and (wr2='1')) then rd1_ack :='0'; rd2_ack :='0'; if (wr1_ack='0' and wr2_ack='0') then state :=21; end if; if (wr1_ack='0' and wr2_ack='1') then state :=22; end if; if (wr1_ack='1' and wr2_ack='0') then state :=23; end if; if (wr1_ack='1' and wr2_ack='1') then state :=24; end if; end if; case state is when 0 => addr1_i := 0; addr2_i := 0; data1_out <="00000000"; data2_out <="00000000"; wr1_ack :='0'; wr2_ack :='0'; rd1_ack :='0'; rd2_ack :='0'; when 1 => addr1_i := conv_integer(addr1); data1_out <= ram(addr1_i) ; rd1_ack := '1'; when 2 => if(addr1_i /= size) then addr1_i := addr1_i +1; else addr1_i := 0; end if; data1_out <=ram(addr1_i); rd1_ack :='1'; when 3 => addr2_i := conv_integer(addr2); data2_out <= ram(addr2_i) ; rd2_ack := '1'; when 4 => if(addr2_i /= size) then addr2_i := addr2_i +1; else addr2_i := 0; end if; data2_out <=ram(addr2_i); rd2_ack :='1'; when 5 => addr1_i := conv_integer(addr1); ram(addr1_i) <= data1_in ; wr1_ack := '1'; when 6 => if(addr1_i /= size) then addr1_i := addr1_i +1; else addr1_i := 0; end if; ram(addr1_i) <= data1_in ; wr1_ack :='1'; when 7 => addr2_i := conv_integer(addr2); ram(addr2_i) <= data2_in ; wr2_ack := '1'; when 8 => if(addr2_i /= size) then addr2_i := addr2_i +1; else addr2_i := 0; end if; ram(addr2_i) <= data2_in ; wr2_ack :='1'; when 9 => addr1_i := conv_integer(addr1); addr2_i := conv_integer(addr2); data1_out <= ram(addr1_i) ; data2_out <= ram(addr2_i) ; rd1_ack := '1'; rd2_ack := '1'; when 10 => addr1_i := conv_integer(addr1); if(addr2_i /= size) then addr2_i := addr2_i +1; else addr2_i := 0; end if; data1_out <= ram(addr1_i) ; data2_out <= ram(addr2_i) ; rd1_ack := '1'; rd2_ack := '1'; when 11 => if(addr1_i /= size) then addr1_i := addr1_i +1; else addr1_i := 0; end if; addr2_i := conv_integer(addr2); data1_out <= ram(addr1_i) ; data2_out <= ram(addr2_i) ; rd1_ack := '1'; rd2_ack := '1'; when 12 => if(addr1_i /= size) then addr1_i := addr1_i +1; else addr1_i := 0; end if; if(addr2_i /= size) then addr2_i := addr2_i +1; else addr2_i := 0; end if; data1_out <= ram(addr1_i) ; data2_out <= ram(addr2_i) ; rd1_ack := '1'; rd2_ack := '1'; when 13 => addr1_i := conv_integer(addr1); addr2_i := conv_integer(addr2); if(addr1_i = addr2_i) then data1_out <= data2_in; ram(addr2_i) <= data2_in; else data1_out <= ram(addr1_i) ; ram(addr2_i) <= data2_in ; end if ; rd1_ack :='1'; wr2_ack :='1'; when 14 => addr1_i := conv_integer(addr1); if(addr2_i /= size) then addr2_i := addr2_i +1; else addr2_i := 0; end if; if(addr1_i = addr2_i) then data1_out <= data2_in; ram(addr2_i) <= data2_in; else data1_out <= ram(addr1_i) ; ram(addr2_i) <= data2_in ; end if ; rd1_ack :='1'; wr2_ack :='1'; when 15 => if(addr1_i /= size) then addr1_i := addr1_i +1; else addr1_i := 0; end if; addr2_i := conv_integer(addr2); if(addr1_i = addr2_i) then data1_out <= data2_in; ram(addr2_i) <= data2_in; else data1_out <= ram(addr1_i) ; ram(addr2_i) <= data2_in ; end if ; rd1_ack :='1'; wr2_ack :='1'; when 16 => if(addr1_i /= size) then addr1_i := addr1_i +1; else addr1_i := 0; end i