This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev 0.1 / Apr. 2011 1
CI-MCP Specification
4GB e-NAND Flash + 4Gb Mobile DDR
Rev 0.1 / Apr. 2011 2
Preliminary
H9DP32A4JJMCGR series
e-NAND 4GB(x8) / Mobile DDR 4Gb(x32 2CS)
Document Title
CI-MCP
4GB(x8) e-NAND / 4Gb (64Mb x32 2/CS 2CKE) Mobile DDR
Revision History
Revision No. History Draft Date Remark
0.1
Initial Draft
- 4GB e-NAND Flash F-Die
- 2Gb mobile DDR A-Die
Apr. 2011 Preliminary
Rev 0.1 / Apr. 2011 3
Preliminary
H9DP32A4JJMCGR series
e-NAND 4GB(x8) / Mobile DDR 4Gb(x32 2CS)
FEATURES
[ CI-MCP ]
● Operation Temperature
- -25
o
C ~ 85
o
C
● Packcage
- 153-ball FBGA - 11.5x13mm
2
, 1.0t, 0.5mm pitch
- Lead & Halogen Free
[ e-NAND Flash ]
● Packaged NAND flash memory with
MultiMediaCard interface
● High capacity memory access
● eMMC/MultiMediaCard system specification,
compliant with V4.41
● Full backward compatibility with previous
MultiMediaCard system specification
● Bus mode
- High-speed MultiMediaCard protocol.
- Three different data bus widths:
1 bit, 4 bits,8 bits.
- Data transfer rate: up to 104Mbyte/s
- DDR mode supported
● Operating voltage range:
- V
CCQ
= 1.7~1.95V/2.7V~3.6V
- V
CC
= 3.3V
● Error free memory access
- Internal error correction code
- Internal enhanced data management
algorithm (wear levelling, bad block
management, garbage collection)
- Possibility for the host to make sudden
power failure safe-update operations for
data content
● Security
- Password protection of data
- Security Erase
- Security Trim
- Secure bad block management
- Built-in write protection
● Boot
- Simple boot sequence method
● Power saving
- Enhanced power saving method by
introducing sleep functionality
● Partition management with enhanced storage.
● Hardware reset supported
[ DDR SDRAM ]
● Double Data Rate architecture
- two data transfer per clock cycle
● x32 bus width
● Supply Voltage
- VDD / VDDQ = 1.7 - 1.95 V
● Memory Cell Array
- 16Mb x 4Bank x 32 I/O x 2 Die
● Bidirectional data strobe (DQS)
● Input data mask signal (DQM)
● Input Clock
- Differential Clock Inputs (CK, /CK)
● MRS, EMRS
- JEDEC Standard guaranteed
● CAS Latency
- Programmable CAS latency 2 or 3 supported
● Burst Length
- Programmable burst length 2 / 4 / 8 with both sequen
tial and interleave mode
Rev 0.1 / Apr. 2011 4
Preliminary
H9DP32A4JJMCGR series
e-NAND 4GB(x8) / Mobile DDR 4Gb(x32 2CS)
ORDERING INFORMATION
Part Number
Memory
Combination
Operation
Voltage
Density Speed Package
H9DP32A4JJMCGR-KEM
e-NAND Flash
mobile DDR
3.3V
1.8V
4GB (x8)
4Gb (64Mb x32 x 2dies)
45ns
DDR400
153Ball FBGA
(Lead & HalogenFree)
Rev 0.1 / Apr. 2011 5
Preliminary
H9DP32A4JJMCGR series
e-NAND 4GB(x8) / Mobile DDR 4Gb(x32 2CS)
153Ball ASSIGNMENT - (4GB+4Gb / eMMC4.41 + x32 LPDDR, 2CS)
VDDQ
DM2
DQ17
DQ19 DQ20
DQ22
DQ8
DQ10
CLK
DM1
VDDQ
DQ12
DQ13
DM0
DQS3
1
2 3 4 5 6 7 8 9 10 11 12 13 14
DNU
DQ6
DQ7
VDDQ
DQ18 DQ16
DQS2
DQ23
DQ9
DQ11
CLK#
VSSQ
d
DQS1
DQ14 DQ15
DQ26
VSSd
DQS0DQ0 DQ4
DQ3 DQ5
VDDQ
DQ1
DQ2
VDD
CMD
NC
VCCQ
VSSd VDDI
IO1IO0
IO3
IO2
NC
NC
DQ27
DQ24
DQ25
DQ28
DQ29
DQ30
VDDQ
A0
DQ31
VSSm
VDD
A2
A3
A1
A9
A7A6
A8A11
VSSd
VDD
A5
A12
CAS#
A4
BA1
RAS#
DM3
VSSm
DNU
DNU
IO6 IO7
CLK
NC NC
VSSQ
d
NC
CKE1
VDDQ
CKE0
A10
VSSQ
d
WE#
IO4 IO5
NC
VCCQ
VSSd
VDD
NC
VSSQ
d
NC
A13
VSSd VDD
BA0
DNU
DRAM Commend / Address DRAM Data IO Power (DRAM : VDD,VDDQ / eMMC : VCC,VCCQ)
Ground (DRAM : VSSd,VSSQd / eMMC : VSSm)
eMMC Command / IO
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC NC
NC
NC
NC
VSSQ
d
VCC
NC
VSSm
NC
VCC
VCCVSSmNCNC
NC
NC
VSSm
VCC
RST#
DQ21
VSSQ
d
VSSQ
d
VDDQ
VSSQ
d
VDDQ
VDDQ
NC
NC
NC
NC
NC
CS1#
CS0#
VSSmVCCQ
VCCQ
VSSmVCCQ
VSSm
TQ
VSSQ
d
VSSm
A
B
C
D
E
F
G
H
J
K
L
M
N
P
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Top View
153ball 11.5x13 CI-MCP
(e-NAND X8 + Mobile DDR X32)
