H9TQ32A4GTMCUR_Rev0.1.pdf

This document is a general product description and is subject to change without notice. SK hynix does not assume any responsibility

for use of circuits described. No patent licenses are implied.

Rev 0.1 / Jul. 2016 1

eMCP Specification

4GB eMMC (x8)

+ 4Gb LPDDR3 (x32)

Rev 0.1 / Jul. 2016 2

Rev 0.1 / Jul. 2016 3

● Operation Temperature

- (-25)

● Package

- 221-ball FBGA

- 11.5x13.0mm

• Operating voltage range

• Temperature

- Operation (-25

C )

- HS200

- HPI, BKOPS

- Partitioning, RPMB

- Discard, Trim, Erase, Sanitize, Secure TRIM,

- Write protect, Lock / Unlock

- PON, Sleep / Awake

- Reliable write

- HW / SW Reset

• Double data rate architecture for command, address and

data Bus;

rising and falling edge of the clock

- two data accesses per clock cycle

• Differential clock inputs (CK_t, CK_c)

• Bi-directional differential data strobe (DQS_t, DQS_c)

tional differential data strobe (DQS_t, DQS_c)

• Programmable RL (Read Latency) and WL (Write Latency)

• Programmable burst length: 8

• Auto refresh and self refresh supported

• All bank auto refresh and per bank auto refresh supported

• Auto TCSR (Temperature Compensated Self Refresh)

• PASR (Partial Array Self Refresh) by Bank Mask and Segment

• DS (Drive Strength)

• ZQ (Calibration)

• ODT (On Die Termination)

Rev 0.1 / Jul. 2016 4

Rev 0.1 / Jul. 2016 5

H9TQ32A4GTMCUR-KUM

eMMC

LPDDR3

4GB (x8)