ram.rar_RAM FIFO_RAM VHDL_fifo 16 8_vhdl fifo component

---------------------------------ram------------------------------ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ram16by4 is Port ( rw : in std_logic; en_l : in std_logic; datain : in std_logic_vector(3 downto 0); addr : in std_logic_vector(3 downto 0); dataout : out std_logic_vector(3 downto 0)); end ram16by4; architecture Behavioral of ram16by4 is subtype wtype is STD_LOGIC_VECTOR (3 downto 0); type mem_type is array (15 downto 0) of wtype; signal memory:mem_type; function conv_integer(x:std_logic_vector) return integer is variable result:integer; begin result:=0; for i in x'range loop if X(i)='1' then result:= result+2**i; else null; end if; end loop; return result; end conv_integer; begin process(en_l,rw,addr) begin if(en_l='0') then if (rw ='0') then memory(conv_integer(addr))<= datain; dataout<="ZZZZ"; elsif (rw ='1') then dataout<=not memory(conv_integer(addr)); end if; else dataout<=(others=>'Z'); end if; end process; end Behavioral; ---------------------------test bench--------------------------- ------------------it is in my record ra---------------------------