LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY cal IS
PORT(inclk:IN STD_LOGIC;
num:IN STD_LOGIC_VECTOR(9 DOWNTO 0);
plus:IN STD_LOGIC;
subt:IN STD_LOGIC;
mult:IN STD_LOGIC;
mdiv:IN STD_LOGIC;
equal:IN STD_LOGIC;
c:IN STD_LOGIC;
onum1,onum2,onum3:OUT STD_LOGIC_VECTOR(0 TO 6)
);
END cal;
ARCHITECTURE behave of cal IS
TYPE state IS (takenum,hundred,ten,one);
SIGNAL viewstep:state;
SIGNAL ktemp:STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL flag:STD_LOGIC;
SIGNAL f1:STD_LOGIC;
SIGNAL acc:STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL reg:STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL keep:STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL ans:STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL dans:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL numbuff:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL vf:STD_LOGIC;
SIGNAL strdiv:STD_LOGIC;
SIGNAL numclk:STD_LOGIC;
SIGNAL clear:STD_LOGIC;
SIGNAL inplus:STD_LOGIC;
SIGNAL insubt:STD_LOGIC;
SIGNAL inmult:STD_LOGIC;
SIGNAL inmdiv:STD_LOGIC;
SIGNAL inequal:STD_LOGIC;
SIGNAL view1,view2,view3:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL cou:STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL clk_gg:STD_LOGIC_VECTOR(11 DOWNTO 0);
SIGNAL clk:STD_LOGIC;
COMPONENT numdecoder IS
PORT(
reset:IN STD_LOGIC;
inclk:IN STD_LOGIC;
innum:IN STD_LOGIC_VECTOR(9 DOWNTO 0);
outnum:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);
outflat:OUT STD_LOGIC;
);
END COMPONENT;
COMPONENT vdecode IS
PORT(
indata:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
outdata:OUT STD_LOGIC_VECTOR(0 TO 6));
END COMPONENT;
COMPONENT diver IS
PORT(
a:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
b:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
clk:IN STD_LOGIC;
str:IN STD_LOGIC;
s:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
y:OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
BEGIN
inum1:numdecoder port map(c,clk,num,numbuff,numclk);
clock:PROCESS(inclk,c)
BEGIN
IF c='1' THEN
clk_gg(11 DOWNTO 0)<="0";
ELSIF inclk'EVENT AND inclk='1' THEN
clk_gg(11 DOWNTO 0)<=clk_gg(11 DOWNTO 0)+1;
END IF;
END PROCESS clock;
clk<=clk_gg(11);
pacecal: PROCESS(c,clk)
BEGIN
IF c='1' THEN
inplus<='0';insubt<='0';inmult<='0';inmdiv<='0';
ELSIF clk'EVENT AND clk='1' THEN
IF plus='1' THEN
inplus<='1';insubt<='0';inmult<='0';inmdiv<='0';
ELSIF subt='1' THEN
inplus<='0';insubt<='1';inmult<='0';inmdiv<='0';
ELSIF mult='1' THEN
inplus<='0';insubt<='0';inmult<='1';inmdiv<='0';
ELSIF mdiv='1' THEN
inplus<='0';insubt<='0';inmult<='0';inmdiv<='1';
END IF;
END IF;
END PROCESS pacecal;
ctrflag:PROCESS(c,clk)
BEGIN
IF c='1' THEN
flag<='0';
ELSIF clk'EVENT AND clk='1' THEN
IF inplus='1' OR insubt='1' OR inmult='1' OR inmdiv='1' THEN
flag<='1';
ELSE flag<='0';
END IF;
END IF;
END PROCESS ctrflag;
ctrfirstnum:PROCESS(c,numclk)
BEGIN
IF c='1' THEN
acc<='00000000';
ELSIF numclk'EVENT AND numclk='0' THEN
IF flag='0' THEN
acc<=acc*"1010"+numbuff;
END IF;
END IF;
END PROCESS ctrfirstnum;
ctrsecondnum:PROCESS(c,numclk)
BEGIN
IF c='1' or clear='1' THEN
reg<="00000000";fl<='0';
ELSIF numclk'EVENT AND numclk='0' THEN
IF flag='1' THEN
fl<='1';
reg<=reg*"1010"+numbuff;
END IF;
END IF;
END PROCESS ctrsecondnum;
ctrclear:PROCESS(c,clk)
BEGIN
IF c='1' THEN
clear<='0';
ELSIF clk'EVENT AND clk='1' THEN
IF plus='1' OR subt='1' THEN
clear<='1';
ELSE clear<='0';
END IF;
END IF;
END PROCESS ctrclear;
ctrinequal:PROCESS(c,clk)
BEGIN
IF c='1' THEN
inequal<='0';
ELSIF clk'EVENT AND clk='1' THEN
IF plus='1' OR subt='1' OR mult='1' OR mdiv='1' OR equal='1' THEN
inequal<='1';
ELSE inequal<='0';
END IF;
END IF;
END PROCESS ctrinequal;
ctrcou;PROCESS(c,inequal)
BEGIN
IF c='1' THEN
cou<="00";
ELSIF inequal'EVENT and inequal='1' THEN
IF cou="10" THEN
cou<=cou;
ELSE cou<=cou+1;
END IF;
END IF;
END PROCESS ctrcou;
ctrcal;PROCESS(c,inequal)
BEGIN
IF c='1' THEN
ans<="00000000";
strdiv<='0';
ELSIF inequal'EVENT and inequal='1' THEN
IF flag='1' THEN
IF inplus='1' THEN
IF cou="10" THEN
ans<=ans+reg;
ELSE ans<=acc+reg;
END IF;
ELSIF insubt='1' THEN
IF cou="10" THEN
ans<=ans-reg;
ELSE ans<=acc-reg;
END IF;
ELSE inmult='1' THEN
IF acc<="00001111"AND reg<="00001111" THEN
ans<=acc(3 downto 0)*reg(3 dowmto 0)
ELSE ans<="00000000";
END IF;
ELSIF inmdiv='1' THEN
strdiv<='1';
END IF;
else strdiv<='0';
END IF;
END IF;
END PROCESS ctrcal;
d1: diver PORT MAP(acc,reg(3 DOWNTO 0),clk,strdiv,dans);
ctrvf:PROCESS(c,equal)
BEGIN
IF c='1' THEN
vf<='0';
ELSIF equal'EVENT AND equal='1' THEN
vf<='1';
END IF;
END PROCESS ctrvf;
ctrkeep:process(c,clk)
BEGIN
IF c='1' THEN
keep<="00000000";
ELSIF clk'EVENT AND clk='0' THEN
IF flag='0'THEN
keep<=acc;
IF flag='1' THEN AND fl='1'AND vf='0' THEN
keep<=reg;
ELSIF flag='1' THEN AND fl='0'AND vf='0'AND cou="10" THEN
keep<=ans;
ELSIF flag='1'AND vf='1' THEN
IF inmdiv='0' THEN
keep<=ans;
ELSE
keep(3 DOWNTO 0)<=dans;
END IF;
END IF;
END IF;
END PROCESS ctrkeep;
ctrview:PROCESS(c,clk)
BEGIN
IF c='1' THEN
view1<="0000";view2<="0000";view3<="0000";
viewstep<=takenum;
ELSIF clk'EVENT AND clk='1' THEN
CASE viewstep IS
WHEN takenum =>
ktemp<=keep;
viewstpe<=hundred;
WHEN hundred =>
IF ktemp>="11001000" THEN
view1<="0010";ktemp<=ktemp-"11001000";
ELSIF ktemp>="01100100" THEN
view1<="0001";ktemp<=ketmp-"01100100";
ELSE view1<="0000";
END IF;
viewstp<=ten;
WHEN ten=>
IF ktemp>="01011010" THEN
view2<="1001";ktemp<=ktemp-"01011010";
ELSIF ktemp>="01010000" THEN
view2<="1000";ktemp<=ktemp-"01010000";
ELSIF ktemp>="01000110" THEN
view2<="0111";ktemp<=ktemp-"01000110";
ELSIF ktemp>="00111100" THEN
view2<="0110";ktemp<=ktemp-"00111100";
ELSIF ktemp>="00110010" THEN
view2<="0101";ktemp<=ktemp-"00110010";
ELSIF ktemp>="00101000" THEN
view2<="0100";ktemp<=ktemp-"00101000";
ELSIF ktemp>="00101000" THEN
view2<="0011";ktemp<=ktemp-"00011110";
ELSIF ktemp>="00101000" THEN
view2<="0010";ktemp<=ktemp-"00010100";
ELSIF ktemp>="00101000" THEN
view2<="0001";ktemp<=ktemp-"00001010";
ELSE view2<="0000";
END IF;
viewstep<=one;
WHEN one =>
view3<=ktemp(3 DOWNTO 0);
viewstep<=takenum;
WHEN OTHERS =>NULL;
END CASE;
END IF;
END PROCESS ctrview;
v1:vdecode PORT MAP(view1,onum1);
v2:vdecode PORT MAP(view2,onum2);
v3:vdecode PORT MAP(view3,onum3);
END behave;