Debug for fit_fastio_pin_reassign program (iteration 1):
I/O delay matrix:-
Comb Reg SU Pin Cout Casc
Clk N/A 44 N/A 44 N/A N/A
Clr N/A 54 N/A 54 N/A N/A
Pre N/A 54 N/A 54 N/A N/A
Ena N/A N/A 32 N/A N/A N/A
Ald N/A 54 N/A 54 N/A N/A
OE N/A N/A N/A 61 N/A N/A
Cin N/A N/A N/A N/A N/A N/A
Casc N/A N/A N/A N/A N/A N/A
Pin 35 N/A 135 N/A N/A N/A
A N/A N/A 25 35 N/A N/A
B N/A N/A N/A N/A N/A N/A
C N/A N/A N/A N/A N/A N/A
D N/A N/A N/A N/A N/A N/A
Global clock delay matrix:-
Comb Reg SU Pin Cout Casc
Clk : N/A 26 52 N/A 38 N/A
Clr : N/A 27 N/A N/A 39 N/A
Pre : N/A 27 N/A N/A 39 N/A
Ena : N/A N/A 22 N/A N/A N/A
Ald : N/A 27 N/A N/A 39 N/A
OE : N/A N/A N/A N/A N/A N/A
Cin : 13 N/A 17 N/A 3 15
Casc: 7 N/A 11 N/A N/A 9
Pin : N/A N/A N/A N/A N/A N/A
A : 23 N/A 27 N/A 12 25
B : 23 N/A 27 N/A 12 25
C : 23 N/A 27 N/A N/A 25
D : 18 N/A 22 N/A N/A 20
I/O delay matrix:-
Comb Reg SU Pin Cout Casc
Clk N/A 44 N/A 44 N/A N/A
Clr N/A 54 N/A 54 N/A N/A
Pre N/A 54 N/A 54 N/A N/A
Ena N/A N/A 32 N/A N/A N/A
Ald N/A 54 N/A 54 N/A N/A
OE N/A N/A N/A 61 N/A N/A
Cin N/A N/A N/A N/A N/A N/A
Casc N/A N/A N/A N/A N/A N/A
Pin 35 N/A 135 N/A N/A N/A
A N/A N/A 25 35 N/A N/A
B N/A N/A N/A N/A N/A N/A
C N/A N/A N/A N/A N/A N/A
D N/A N/A N/A N/A N/A N/A
Global clock delay matrix:-
Comb Reg SU Pin Cout Casc
Clk : N/A 26 52 N/A 38 N/A
Clr : N/A 27 N/A N/A 39 N/A
Pre : N/A 27 N/A N/A 39 N/A
Ena : N/A N/A 22 N/A N/A N/A
Ald : N/A 27 N/A N/A 39 N/A
OE : N/A N/A N/A N/A N/A N/A
Cin : 13 N/A 17 N/A 3 15
Casc: 7 N/A 11 N/A N/A 9
Pin : N/A N/A N/A N/A N/A N/A
A : 23 N/A 27 N/A 12 25
B : 23 N/A 27 N/A 12 25
C : 23 N/A 27 N/A N/A 25
D : 18 N/A 22 N/A N/A 20
Threshold are: for Tsu - 10.600000ns and for Tco - 17.700000ns
Global Tsu=-1(-1.000000), Tco=-1(-1.000000)
Input/output cells:
c -> 42 : IN
clk -> 43 : IN
equal -> 1 : IN
mdiv : IN
mult : IN
num0 : IN
num1 : IN
num2 : IN
num3 : IN
num4 : IN
num5 : IN
num6 : IN
num7 : IN
num8 : IN
num9 : IN
onum10 : OUT
onum11 : OUT
onum12 : OUT
onum13 : OUT
onum14 : OUT
onum15 : OUT
onum16 : OUT
onum20 : OUT
onum21 : OUT
onum22 : OUT
onum23 : OUT
onum24 : OUT
onum25 : OUT
onum26 : OUT
onum30 : OUT
onum31 : OUT
onum32 : OUT
onum33 : OUT
onum34 : OUT
onum35 : OUT
onum36 : OUT
plus : IN
subt : IN
Set clique dont_touch:
Cell: c, rdfbits: 4000005, fast_io bit: 0, periphery: 0,0
Cell: clk, rdfbits: d, fast_io bit: 0, periphery: 0,0
Cell: c~1, rdfbits: 201050, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|sub4:u1|adder:add~62|:11, rdfbits: 50, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|sub4:u1|adder:add~62|:14, rdfbits: 50, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|sub4:u1|adder:add~93|:14, rdfbits: 50, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|sub4:u1|adder:add~116|:14, rdfbits: 50, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:15, rdfbits: 110, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:17, rdfbits: 110, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:19, rdfbits: 110, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:21, rdfbits: 110, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:31, rdfbits: 110, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:32, rdfbits: 110, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:33, rdfbits: 110, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:34, rdfbits: 110, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:35, rdfbits: 110, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:36, rdfbits: 110, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:37, rdfbits: 110, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:38, rdfbits: 110, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:39, rdfbits: 110, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:40, rdfbits: 110, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:41, rdfbits: 110, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:43, rdfbits: 110, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:44, rdfbits: 110, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:45, rdfbits: 110, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:46, rdfbits: 110, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:47, rdfbits: 110, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:48, rdfbits: 110, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:49, rdfbits: 110, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:60, rdfbits: 110, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:61, rdfbits: 110, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:431, rdfbits: 50, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:437, rdfbits: 50, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:443, rdfbits: 50, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:503, rdfbits: 50, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:509, rdfbits: 50, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:515, rdfbits: 50, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:521, rdfbits: 50, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:1053, rdfbits: 50, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:1479, rdfbits: 200050, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:1489, rdfbits: 50, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|~1499~1, rdfbits: 1050, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|~1499~2, rdfbits: 1050, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:1499, rdfbits: 200050, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|~1517~1, rdfbits: 1050, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:1665, rdfbits: 50, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:1666, rdfbits: 50, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:1680, rdfbits: 50, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:1681, rdfbits: 50, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:1695, rdfbits: 50, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:1696, rdfbits: 50, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|~1712~1, rdfbits: 1050, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|~1712~2, rdfbits: 1050, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|~1772~1, rdfbits: 1050, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|~1832~1, rdfbits: 201050, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:1845, rdfbits: 50, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:1846, rdfbits: 50, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:1860, rdfbits: 50, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:1861, rdfbits: 50, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:1875, rdfbits: 50, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:1876, rdfbits: 50, fast_io bit: 0, periphery: 0,0
Cell: |div:d1|:1889, rdfbits: 50, fast_io bit: 0, periphery: 0,0
Cell: equal, rdfbits: d, fast_io bit: 0, periphery: 0,0
Cell: |LPM_ADD_SUB:413|addcore:adder|pcarry2, rdfbits: 50, fast_io bit: 0, periphery: 0,0
Cell: |LPM_ADD_SUB:413|addcore:adder|pcarry3, rdfbits: 50, fast_io bit: 0, periphery: 0,0
Cell: |LPM_ADD_SUB:413|addcore:adder|:133, rdfbits: 50, fast_io bit: 0, periphery: 0,0
Cell: |LPM_ADD_SUB:413|addcore:adder|:137, rdfbits: 200050, fast_io bit: 0, periphery: 0,0
Cell: |LPM_ADD_SUB:413|addcore:adder|~157~1, rdfbits: 1050, fast_io bit: 0, periphery: 0,0
Cell: |LPM_ADD_SUB:413|addcore:adder|~158~1, rdfbits: 1050, fast_io bit: 0, periphery: 0,0
Cell: |LPM_ADD_SUB:609|addcore:adder|pcarry2, rdfbits: 50, fast_io bit: 0, periphery: 0,0
Cell: |LPM_ADD_SUB:609|addcore:adder|pcarry3, rdfbits: 50, fast_io bit: 0, periphery: 0,0
Cell: |LPM_ADD_SUB:609|addcore:adder|:133, rdfbits: 50, fast_io bit: 0, periphery: 0,0
Cell: |LPM_ADD_SUB:609|addcore:adder|:137, rdfbits: 200050, fast_io bit: 0, periphery: 0,0
Cell: |LPM_ADD_SUB:609|addcore:adder|~157~1, rdfbits: 1050, fast_io bit: 0, periphery: 0,0
Cell: |LPM_ADD_SUB:609|addcore:adder|~158~1, rdfbits: 1050, fast_io bit: 0, periphery: 0,0
Cell: |LPM_ADD_SUB:1014|addcore:adder|pcarry1, rdfbits: 50, fast_io bit: 0, periphery: 0,0
Cell: |LPM_ADD_SUB:1014|addcore:adder|pcarry2, rdfbits: 50, fast_io bit: 0, periphery: 0,0
Cell: |LPM_ADD_SUB:1014|add
jisuanqi.rar_calculator vhdl_muxplu_vhdl实现计算器_计算器_计算器设计
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jisuanqi.rar_calculator vhdl_muxplu_vhdl实现计算器_计算器_计算器设计 （500个子文件） 
cal1.acf 15KB cal3.acf 15KB cal2.acf 15KB cal.acf 15KB numdecoder.acf 15KB couter1.acf 15KB vdecode.acf 15KB sub412.acf 15KB add123.acf 15KB fpdiv.acf 15KB mul12.acf 15KB div12.acf 15KB sub41.acf 15KB mux21.acf 15KB sub4.acf 15KB div.acf 15KB s_machine.acf 15KB mul8x8.acf 15KB adder.acf 15KB add12.acf 15KB div84.acf 15KB div1.acf 14KB dfg.acf 14KB sub.acf 14KB add12.cmp 2KB add13.cmp 2KB div1.cmp 2KB subb.cmp 2KB sub.cmp 2KB mult.cmp 2KB rom12.cmp 2KB couter.cmp 1KB cal.cnf 428KB cal(29).cnf 191KB div.cnf 191KB cal(6).cnf 176KB div12(2).cnf 88KB mul8x8(3).cnf 60KB fpdiv.cnf 57KB numdecoder.cnf 51KB cal(28).cnf 51KB mul8x8(5).cnf 49KB mul8x8(7).cnf 36KB mul8x8(2).cnf 34KB div(5).cnf 29KB cal(33).cnf 29KB sub4.cnf 29KB cal(38).cnf 28KB cal(35).cnf 28KB vdecode.cnf 28KB mul8x8(10).cnf 28KB mul8x8(8).cnf 26KB s_machine.cnf 25KB mul8x8(11).cnf 25KB mul8x8(9).cnf 25KB mul8x8(6).cnf 25KB mul8x8(4).cnf 23KB cal(20).cnf 22KB mul12(4).cnf 22KB cal(7).cnf 20KB mul8x8(12).cnf 19KB cal(1).cnf 19KB cal(9).cnf 18KB cal(8).cnf 18KB cal(24).cnf 16KB mul12(8).cnf 16KB couter1(3).cnf 15KB add123(2).cnf 14KB cal(27).cnf 14KB cal(12).cnf 14KB mul12(7).cnf 14KB cal(23).cnf 14KB cal(10).cnf 13KB cal(2).cnf 13KB mux21(2).cnf 13KB add123(3).cnf 13KB cal(13).cnf 13KB mul8x8(1).cnf 13KB fpdiv(1).cnf 13KB cal(22).cnf 13KB mul12(6).cnf 13KB cal(21).cnf 12KB mul12(5).cnf 12KB cal(19).cnf 12KB mul12(3).cnf 12KB div12(1).cnf 12KB div12(15).cnf 11KB sub4(2).cnf 11KB cal(5).cnf 11KB mul12(9).cnf 11KB cal(25).cnf 11KB sub412(2).cnf 10KB div12(12).cnf 10KB div(10).cnf 10KB sub4(8).cnf 10KB sub41(2).cnf 10KB div12(9).cnf 9KB div(1).cnf 9KB cal(30).cnf 9KB couter1(2).cnf 9KB共 500 条
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