<html>
<head>
<title>Sample Waveforms for PLL_ctrl.v </title>
</head>
<body>
<h2><CENTER>Sample behavioral waveforms for design file PLL_ctrl.v </CENTER></h2>
<P>The following waveforms show the behavior of altpll megafunction for the chosen set of parameters in design PLL_ctrl.v. The design PLL_ctrl.v has Cyclone II PLL_TYPE pll configured in NORMAL mode The primary clock input to the PLL is INCLK0, with clock period 40000 ps. Output port LOCKED will go high when the PLL locks to the input clock. </P>
<CENTER><img src=PLL_ctrl_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing NORMAL mode operation. </CENTER></P>
<P><FONT size=3>When input port ARESET is asserted, it will cause the LOCKED port and all CLK outputs to drop to zero. The PLL will relock to the input clock when this port is deasserted. </P>
<P></P>
</body>
</html>
SDRAM.rar_VERILOG SDRAM_sdram de2_sdram verilog
版权申诉
168 浏览量
2022-09-20
20:19:36
上传
评论
收藏 151KB RAR 举报
SDRAM.rar （46个子文件） 
SDRAM 
PLL_ctrl_wave0.jpg 775KB
PLL_ctrl.qip 542B datagene.v.bak 3KB sdr_test.flow.rpt 6KB sdr_test.map.rpt 25KB sdr_test.map.summary 665B PLL_ctrl_bb.v 14KB sdram_top.v 3KB uart_sdramtop.v 1KB sys_ctrl.v 2KB uart_ctrl.v 1KB db sdr_test.eco.cdb 161B sdr_test.sld_design_entry.sci 154B sdr_test.db_info 137B prev_cmp_sdr_test.map.qmsg 60KB sdr_test.map_bb.hdb 6KB sdr_test.map.qmsg 40KB sdr_test.tis_db_list.ddb 174B sdr_test.cmp.rdb 3KB prev_cmp_sdr_test.qmsg 60KB sdr_test.cbx.xml 90B sdr_test.v 5KB uart_speed_select.v 2KB uart_tx.v 2KB sdr_test1.v 5KB PLL_ctrl.ppf 617B incremental_db compiled_partitions README 653B sdfifo_ctrl.v.bak 2KB uart_sdramtop.v.bak 1KB sdr_test.qpf 1KB sdram_ctrl.v.bak 10KB sdr_test.qsf 3KB sdr_test.v.bak 2KB sdram_wr_data.v 2KB PLL_ctrl_inst.v 162B PLL_ctrl.bsf 4KB sdram_cmd.v 4KB datagene.v 3KB sdr_test.qws 534B PLL_ctrl.v 18KB sdram_top.v.bak 3KB
PLL_ctrl_waveforms.html 869B sdfifo_ctrl.v 2KB sdram_ctrl.v 10KB uart_ctrl.v.bak 1KB sys_ctrl.v.bak 2KB
评论0