jiafaqi.rar_VHDL 加法器_全加器

library ieee; use ieee.std_logic_1164.all; entity adder4 is port(a,b : in std_logic_vector; cin : in std_logic; s : out std_logic_vector; cout : out std_logic); end adder4; architecture st_adder4 of adder4 is component fa port(a,b,cin : in std_logic; s,cout : out std_logic); end component; signal t1,t2,t3 : std_logic; begin fa1 : fa port map(a(0),b(0),cin,s(0),t1); fa2 : fa port map(a(1),b(1),t1,s(1),t2); fa3 : fa port map(a(2),b(2),t2,s(2),t3); fa4 : fa port map(a(3),b(3),t3,s(3),cout); end st_adder4;