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EDA中用一位全加器,设计四位全加器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY addr1 IS
PORT(x,y, cin: IN STD_LOGIC;
sum,count : OUT STD_LOGIC );
END addr1;
ARCHITECTURE dataflow OF addr1 IS
BEGIN
sum <= x XOR y XOR cin;
count <= (x AND y) OR (x AND cin) OR (y AND cin) ;
END dataflow;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY addr4 IS
PORT (a,b:IN std_logic_vector(0 to 3);
cin: IN std_logic;
s: OUT std_logic_vector(0 to 3);
co:OUT std_logic);
END addr4;
ARCHITECTURE full OF addr4 IS
COMPONENT addr1
PORT(x,y,cin:IN STD_LOGIC;
sum,count:OUT STD_LOGIC);
End COMPONENT;
SIGNAL c: std_logic_vector(1 to 3);
begin
u0:addr1 PORT MAP (a(0),b(0),cin,s(0),c(1));
u1:addr1 PORT MAP (a(1),b(1),c(1),s(1),c(2));
u2:addr1 PORT MAP (a(2),b(2),c(2),s(2),c(3));
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY addr1 IS
PORT(x,y, cin: IN STD_LOGIC;
sum,count : OUT STD_LOGIC );
END addr1;
ARCHITECTURE dataflow OF addr1 IS
BEGIN
sum <= x XOR y XOR cin;
count <= (x AND y) OR (x AND cin) OR (y AND cin) ;
END dataflow;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY addr4 IS
PORT (a,b:IN std_logic_vector(0 to 3);
cin: IN std_logic;
s: OUT std_logic_vector(0 to 3);
co:OUT std_logic);
END addr4;
ARCHITECTURE full OF addr4 IS
COMPONENT addr1
PORT(x,y,cin:IN STD_LOGIC;
sum,count:OUT STD_LOGIC);
End COMPONENT;
SIGNAL c: std_logic_vector(1 to 3);
begin
u0:addr1 PORT MAP (a(0),b(0),cin,s(0),c(1));
u1:addr1 PORT MAP (a(1),b(1),c(1),s(1),c(2));
u2:addr1 PORT MAP (a(2),b(2),c(2),s(2),c(3));







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