module LTC_ADC( Clk, Rst,
AMP_nCS, AMP_SHDN, SPI_MOSI,
SPI_SCK,
AD_CONV, SPI_MISO
);
input Clk, Rst;
output wire AMP_SHDN;
output reg AMP_nCS, SPI_MOSI;
output reg SPI_SCK;
output reg AD_CONV;
input SPI_MISO;
//---------------------------------------------------------------------------------------------
assign AMP_SHDN = 1'b0;
parameter AMP_GAIN = 8'h11;
parameter STA_IDLE = 3'b001;
parameter STA_AMP = 3'b010;
parameter STA_ADC = 3'b100;
reg [2:0] Cur_State, Nxt_State;
reg [6:0] Cnter;
reg [13:0] Reg_ADC_CH1, Reg_ADC_CH2;
reg [7:0] Reg_AMP_Gain;
always @( posedge Clk )
begin
if( Rst )
Cur_State <= STA_IDLE;
else
Cur_State <= Nxt_State;
end
always @( Cur_State or Cnter )
begin
case( Cur_State )
STA_IDLE :
begin
if( Cnter == 7'd2 )
Nxt_State = STA_AMP;
else
Nxt_State = STA_IDLE;
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