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:: BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
:: INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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::****************************************************************************
:: ____ ____
:: / /\/ /
:: /___/ \ / Vendor : Xilinx
:: \ \ \/ Version : 3.92
:: \ \ Application : MIG
:: / / Filename : readme.txt
:: /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:57 $
:: \ \ / \ Date Created : Fri Feb 06 2009
:: \___\/\___\
::
:: Device : Spartan-6
:: Design Name : DDR/DDR2/DDR3/LPDDR
:: Purpose : Information about par folder
:: Reference :
:: Revision History :
::****************************************************************************
This folder has the batch files to synthesize using XST or Synplify Pro and
implement the design either in "Command Line Mode" or in "GUI Mode".
Steps to run the design using the ise_flow (batch mode):
1. Executing the "ise_flow.bat" file synthesizes the design using XST or
Synplify Pro and does implement the design.
a. First it removes the XST/Synplify Pro report files, implementation
files, supporting scripts, the generated chipscope designs (if
enabled) and the ISE project files (if exist any on previous runs)
b. Synthesizes the design either with XST or Synplicity
c. Implements the design with ISE.
2. After the design is run, it creates ise_flow_results.txt file that will have
the ISE log information.
Steps to run the design using the create_ise (GUI mode - for XST cases only):
1. This file will appear for XST cases only.
2. On executing the "create_ise.bat" file creates "test.xise" project file
and set all the properties of the design selected.
3. The design can be implemented in ISE Projnav GUI by invoking the "test.xise" project file.
4. In Linux operating systems, test.xise project can be invoked by executing the command
'ise test.xise' from the terminal.
Other files in PAR folder :
* "example_top.ucf" file is the constraint file for the design.
It has clock constraints, location constraints and IO standards.
* "mem_interface_top.ut" file has the options for the Configuration file
generation i.e. the "example_top.bit" file to run in batch mode.
* "rem_files.bat" file has all the ISE/Synplify Pro generated report files,
implementation files, supporting scripts, the generated chipscope designs
(if enabled) and the ISE project files.
* "set_ise_prop.tcl" file has all the properties that are to be
set in GUI mode.
* "ise_run.txt" file has synthesis options for the XST tool.
This file is used for batch mode.
* "icon_coregen.xco", "ila_coregen.xco" and "vio_coregen.xco"files are used to
generate ChipScope ila,vio and icon EDIF/NGC files. In order to generate the
EDIF/NGC files, you must execute the following commands before starting
synthesis and PAR.
coregen -b ila_coregen.xco
coregen -b icon_coregen.xco
coregen -b vio_coregen.xco
Note : When you generate the design using "Debug Signals for Memory Controller"
option Enable, the above mentioned ChipScope coregen commands are printed
into ise_flow.bat and create_ise.bat files. The example_top rtl file
will have the design debug signals portmapped to vio and icon
ChipScope modules.
* At the start of a Chip Scope Analyzer project, all of the signals in
every core have generic names. "example_top.cdc" is a file that contains
all the signal names of all cores. Upon importing this file, signal names are
renamed to the specified names in "example_top.cdc" file. This file will work
for the generated designs from MIG. If any of the design parameter values
are changed after generating the design, this file will not work.
For Multiple Controller designs, signal names provided in CDC file are of
the controller that is enabled for Debug in the GUI.
synth folder:
1. mem_interface_top_synp.sdc
2. script_synp.tcl
3. example_top.prj
4. example_top.lso
mem_interface_top_synp.sdc and script_synp.tcl files are being used by
Synplify Pro and example_top.prj and example_top.lso are being used by XST.
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11_ddr3_test.zip_Spartan-6_Xilinx_ddr3_ddr3 xilinx_xilinx ddr3 (209个子文件)
icon.asy 283B
rem_files.bat 8KB
rem_files.bat 8KB
ise_flow.bat 4KB
ise_flow.bat 4KB
isim.bat 3KB
isim.bat 3KB
create_ise.bat 3KB
create_ise.bat 3KB
makeproj.bat 28B
makeproj.bat 28B
example_top.bgn 9KB
example_top.bit 454KB
example_top.bld 93KB
example_top.cdc 14KB
mig_39_2.cdc 13KB
ila.cdc 11KB
vio.cdc 553B
coregen.cgc 68KB
coregen.cgc 63KB
coregen.cgp 522B
coregen.cgp 520B
example_top.cmd_log 2KB
ax516.cpj 99KB
example_top_pad.csv 16KB
sim.do 5KB
sim.do 5KB
example_top.drc 2KB
test.gise 12KB
icon.gise 1KB
mig_39_2.gise 1KB
vio.gise 1KB
ila.gise 1KB
usage_statistics_webtalk.html 229KB
example_top_envsettings.html 14KB
example_top_summary.html 9KB
par_usage_statistics.html 4KB
mig_39_2_summary.html 3KB
coregen.log 2KB
webtalk.log 777B
mig_39_2.lso 6B
example_top.lso 6B
netlist.lst 377B
example_top_map.map 10KB
example_top_map.mrp 62KB
example_top_guide.ncd 1.02MB
example_top.ncd 1.02MB
example_top_map.ncd 551KB
example_top.ngc 1.61MB
ila.ngc 488KB
icon.ngc 41KB
vio.ngc 21KB
example_top.ngd 2.92MB
example_top_map.ngm 5.42MB
example_top.ngr 2.31MB
example_top.pad 16KB
example_top.par 21KB
example_top.pcf 496KB
ug388.pdf 2.07MB
ug416.pdf 78KB
mig.prj 3KB
mig.prj 3KB
mig.prj 3KB
mig_39_2.prj 1KB
example_top.prj 1KB
example_top.prj 1KB
mig_39_2.prj 1KB
mig_39_2.prj 457B
test.projectmgr 7KB
mig_39_2.projectmgr 4KB
example_top.ptwx 23KB
work.sdbl 1.52MB
work.sdbx 628B
mem_interface_top_synp.sdc 2KB
mem_interface_top_synp.sdc 1KB
example_top.stx 0B
example_top.syr 588KB
set_ise_prop.tcl 6KB
set_ise_prop.tcl 5KB
mig_39_2_xmdf.tcl 3KB
isim.tcl 3KB
isim.tcl 3KB
script_synp.tcl 2KB
icon_xmdf.tcl 2KB
vio_xmdf.tcl 2KB
ila_xmdf.tcl 2KB
script_synp.tcl 1KB
example_top.twr 246KB
example_top.twx 281KB
example_top_pad.txt 66KB
readme.txt 6KB
readme.txt 5KB
readme.txt 5KB
mig_39_2_flist.txt 5KB
log.txt 3KB
log.txt 2KB
datasheet.txt 2KB
datasheet.txt 2KB
mig_39_2_readme.txt 2KB
ise_run.txt 1KB
共 209 条
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- xing1321412022-08-10资源很实用,内容详细,值得借鉴的内容很多,感谢分享。
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