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i2c_latest[1].tar.gz_I2C opencores_The Bus_wishbone_wishbone i2c
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2022-09-19
18:44:46
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I2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange between devices. It is primarily used in the consumer and telecom market sector and as a board level communications protocol. The OpenCores I2C Master Core provides an interface between a Wishbone Master and an I2C bus.
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i2c_latest[1].tar.gz (59个子文件)
i2c
tags
asyst_3
rtl
verilog
i2c_master_top.v 10KB
i2c_master_bit_ctrl.v 16KB
timescale.v 23B
i2c_master_byte_ctrl.v 10KB
i2c_master_defines.v 3KB
asyst_2
rtl
verilog
i2c_master_top.v 10KB
i2c_master_bit_ctrl.v 16KB
timescale.v 23B
i2c_master_byte_ctrl.v 10KB
i2c_master_defines.v 3KB
rel_1
software
include
oc_i2c_master.h 6KB
rtl
vhdl
i2c_master_top.vhd 13KB
i2c_master_byte_ctrl.vhd 12KB
tst_ds1621.vhd 7KB
i2c_master_bit_ctrl.vhd 17KB
readme 789B
I2C.VHD 13KB
verilog
i2c_master_top.v 10KB
i2c_master_bit_ctrl.v 16KB
timescale.v 23B
i2c_master_byte_ctrl.v 10KB
i2c_master_defines.v 3KB
sim
i2c_verilog
run
ncverilog.key 5B
bench.vcd 5.07MB
run 597B
ncverilog.log 5KB
doc
i2c_specs.pdf 207KB
src
I2C_specs.doc 454KB
bench
verilog
i2c_slave_model.v 11KB
wb_master_model.v 5KB
tst_bench_top.v 13KB
first
tst_ds1621.vhd 7KB
I2C.VHD 13KB
branches
web_uploads
i2c_rev03.pdf 77KB
index_orig.shtml 2KB
Block.gif 8KB
index.shtml 2KB
trunk
software
include
oc_i2c_master.h 6KB
rtl
vhdl
i2c_master_top.vhd 15KB
i2c_master_byte_ctrl.vhd 12KB
tst_ds1621.vhd 7KB
i2c_master_bit_ctrl.vhd 24KB
readme 789B
I2C.VHD 13KB
verilog
i2c_master_top.v 10KB
i2c_master_bit_ctrl.v 21KB
timescale.v 23B
i2c_master_byte_ctrl.v 10KB
i2c_master_defines.v 3KB
sim
i2c_verilog
run
ncverilog.key 5B
bench.vcd 5.07MB
run 514B
ncverilog.log 5KB
doc
i2c_specs.pdf 207KB
src
I2C_specs.doc 454KB
bench
verilog
i2c_slave_model.v 11KB
spi_slave_model.v 4KB
wb_master_model.v 5KB
tst_bench_top.v 14KB
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- 1
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