MSP430x5xx and MSP430x6xx Family
User's Guide
Literature Number: SLAU208O
June 2008–Revised May 2015
Contents
Preface....................................................................................................................................... 52
1 System Resets, Interrupts, and Operating Modes, System Control Module (SYS)....................... 54
1.1 System Control Module (SYS) Introduction ............................................................................ 55
1.2 System Reset and Initialization........................................................................................... 55
1.2.1 Device Initial Conditions After System Reset.................................................................. 57
1.3 Interrupts .................................................................................................................... 57
1.3.1 (Non)Maskable Interrupts (NMIs) ............................................................................... 58
1.3.2 SNMI Timing ....................................................................................................... 59
1.3.3 Maskable Interrupts ............................................................................................... 59
1.3.4 Interrupt Processing............................................................................................... 59
1.3.5 Interrupt Nesting................................................................................................... 61
1.3.6 Interrupt Vectors................................................................................................... 61
1.3.7 SYS Interrupt Vector Generators................................................................................ 62
1.4 Operating Modes ........................................................................................................... 63
1.4.1 Entering and Exiting Low-Power Modes LPM0 Through LPM4............................................. 66
1.4.2 Entering and Exiting Low-Power Modes LPMx.5 ............................................................. 66
1.4.3 Extended Time in Low-Power Modes .......................................................................... 67
1.5 Principles for Low-Power Applications .................................................................................. 68
1.6 Connection of Unused Pins............................................................................................... 69
1.7 Reset Pin (RST/NMI) Configuration ..................................................................................... 69
1.8 Configuring JTAG Pins .................................................................................................... 70
1.9 Boot Code ................................................................................................................... 70
1.10 Bootstrap Loader (BSL) ................................................................................................... 70
1.11 Memory Map – Uses and Abilities ....................................................................................... 71
1.11.1 Vacant Memory Space .......................................................................................... 72
1.11.2 JTAG Lock Mechanism Using the Electronic Fuse .......................................................... 72
1.12 JTAG Mailbox (JMB) System ............................................................................................ 72
1.12.1 JMB Configuration ............................................................................................... 72
1.12.2 JMBOUT0 and JMBOUT1 Outgoing Mailbox................................................................. 72
1.12.3 JMBIN0 and JMBIN1 Incoming Mailbox....................................................................... 73
1.12.4 JMB NMI Usage .................................................................................................. 73
1.13 Device Descriptor Table................................................................................................... 73
1.13.1 Identifying Device Type.......................................................................................... 74
1.13.2 TLV Descriptors .................................................................................................. 75
1.13.3 Peripheral Discovery Descriptor ............................................................................... 76
1.13.4 CRC Computation................................................................................................ 80
1.13.5 Calibration Values................................................................................................ 81
1.13.6 Temperature Sensor Calibration for Devices With CTSD16 ............................................... 82
1.14 SFR Registers .............................................................................................................. 83
1.14.1 SFRIE1 Register ................................................................................................. 84
1.14.2 SFRIFG1 Register ............................................................................................... 85
1.14.3 SFRRPCR Register.............................................................................................. 87
1.15 SYS Registers .............................................................................................................. 88
1.15.1 SYSCTL Register ................................................................................................ 89
1.15.2 SYSBSLC Register .............................................................................................. 90
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1.15.3 SYSJMBC Register .............................................................................................. 91
1.15.4 SYSJMBI0 Register.............................................................................................. 92
1.15.5 SYSJMBI1 Register.............................................................................................. 92
1.15.6 SYSJMBO0 Register ............................................................................................ 93
1.15.7 SYSJMBO1 Register ............................................................................................ 93
1.15.8 SYSUNIV Register ............................................................................................... 94
1.15.9 SYSSNIV Register ............................................................................................... 95
1.15.10 SYSRSTIV Register ............................................................................................ 96
1.15.11 SYSBERRIV Register .......................................................................................... 97
2 Power Management Module and Supply Voltage Supervisor ................................................... 98
2.1 Power Management Module (PMM) Introduction ...................................................................... 99
2.2 PMM Operation ........................................................................................................... 101
2.2.1 V
CORE
and the Regulator......................................................................................... 101
2.2.2 Supply Voltage Supervisor and Monitor ...................................................................... 101
2.2.3 Supply Voltage Supervisor and Monitor - Power-Up........................................................ 107
2.2.4 Increasing V
CORE
to Support Higher MCLK Frequencies ................................................... 108
2.2.5 Decreasing V
CORE
for Power Optimization .................................................................... 109
2.2.6 Transition From LPM3 and LPM4 Modes to AM ............................................................ 109
2.2.7 LPM3.5 and LPM4.5 ............................................................................................ 109
2.2.8 Brownout Reset (BOR), Software BOR, Software POR.................................................... 110
2.2.9 SVS and SVM Performance Modes and Wakeup Times .................................................. 110
2.2.10 PMM Interrupts.................................................................................................. 113
2.2.11 Port I/O Control ................................................................................................. 113
2.2.12 Supply Voltage Monitor Output (SVMOUT, Optional)...................................................... 113
2.3 PMM Registers............................................................................................................ 114
2.3.1 PMMCTL0 Register.............................................................................................. 115
2.3.2 PMMCTL1 Register.............................................................................................. 116
2.3.3 SVSMHCTL Register............................................................................................ 117
2.3.4 SVSMLCTL Register ............................................................................................ 118
2.3.5 SVSMIO Register ................................................................................................ 119
2.3.6 PMMIFG Register................................................................................................ 120
2.3.7 PMMRIE Register................................................................................................ 122
2.3.8 PM5CTL0 Register .............................................................................................. 123
3 Battery Backup System ..................................................................................................... 124
3.1 Battery Backup Introduction ............................................................................................. 125
3.2 Battery Backup Operation ............................................................................................... 125
3.2.1 Activate Access to Backup-Supplied Subsystem............................................................ 126
3.2.2 Manual Switching ................................................................................................ 127
3.2.3 Disable Switching ................................................................................................ 127
3.2.4 Measuring the Supplies ......................................................................................... 127
3.2.5 LPMx.5 and Backup Operation ................................................................................ 127
3.2.6 Resistive Charger................................................................................................ 128
3.3 Battery Backup Registers................................................................................................ 129
3.3.1 BAKCTL Register ................................................................................................ 130
3.3.2 BAKCHCTL Register ............................................................................................ 131
4 Auxiliary Supply System (AUX) .......................................................................................... 132
4.1 Auxiliary Supply System Introduction .................................................................................. 133
4.2 Auxiliary Supply Operation .............................................................................................. 134
4.2.1 Startup............................................................................................................. 135
4.2.2 Switching Control ................................................................................................ 135
4.2.3 Software-Controlled Switching ................................................................................. 135
4.2.4 Hardware-Controlled Switching ................................................................................ 136
4.2.5 Interactions Among f
SYS
, V
CORE
, V
DSYS
, SVM
H
, and AUXxLVL ............................................... 137
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4.2.6 Auxiliary Supply Monitor ........................................................................................ 139
4.2.7 LPMx.5 and Auxiliary Supply Operation ...................................................................... 141
4.2.8 Digital I/Os and Auxiliary Supplies............................................................................. 141
4.2.9 Measuring the Supplies ......................................................................................... 142
4.2.10 Resistive Charger............................................................................................... 143
4.2.11 Auxiliary Supply Interrupts..................................................................................... 143
4.2.12 Software Flow ................................................................................................... 145
4.2.13 Examples of AUX Operation .................................................................................. 146
4.3 AUX Registers............................................................................................................. 148
4.3.1 AUXCTL0 Register .............................................................................................. 149
4.3.2 AUXCTL1 Register .............................................................................................. 150
4.3.3 AUXCTL2 Register .............................................................................................. 151
4.3.4 AUX2CHCTL Register .......................................................................................... 152
4.3.5 AUX3CHCTL Register .......................................................................................... 153
4.3.6 AUXADCCTL Register .......................................................................................... 154
4.3.7 AUXIFG Register ................................................................................................ 155
4.3.8 AUXIE Register .................................................................................................. 156
4.3.9 AUXIV Register .................................................................................................. 157
5 Unified Clock System (UCS)............................................................................................... 158
5.1 Unified Clock System (UCS) Introduction ............................................................................. 159
5.2 UCS Operation............................................................................................................ 161
5.2.1 UCS Module Features for Low-Power Applications......................................................... 161
5.2.2 Internal Very-Low-Power Low-Frequency Oscillator (VLO) ................................................ 161
5.2.3 Internal Trimmed Low-Frequency Reference Oscillator (REFO) .......................................... 162
5.2.4 XT1 Oscillator .................................................................................................... 162
5.2.5 XT2 Oscillator ................................................................................................... 163
5.2.6 Digitally Controlled Oscillator (DCO) .......................................................................... 164
5.2.7 Frequency Locked Loop (FLL) ................................................................................. 165
5.2.8 DCO Modulator .................................................................................................. 166
5.2.9 Disabling FLL Hardware and Modulator ...................................................................... 166
5.2.10 FLL Operation From Low-Power Modes..................................................................... 167
5.2.11 Operation From Low-Power Modes, Requested by Peripheral Modules................................ 167
5.2.12 UCS Module Fail-Safe Operation............................................................................. 168
5.2.13 Synchronization of Clock Signals............................................................................. 171
5.3 Module Oscillator (MODOSC)........................................................................................... 172
5.3.1 MODOSC Operation ............................................................................................ 172
5.4 UCS Registers ............................................................................................................ 173
5.4.1 UCSCTL0 Register .............................................................................................. 174
5.4.2 UCSCTL1 Register .............................................................................................. 175
5.4.3 UCSCTL2 Register .............................................................................................. 176
5.4.4 UCSCTL3 Register .............................................................................................. 177
5.4.5 UCSCTL4 Register .............................................................................................. 178
5.4.6 UCSCTL5 Register .............................................................................................. 179
5.4.7 UCSCTL6 Register .............................................................................................. 181
5.4.8 UCSCTL7 Register .............................................................................................. 183
5.4.9 UCSCTL8 Register .............................................................................................. 184
5.4.10 UCSCTL9 Register ............................................................................................. 185
6 CPUX .............................................................................................................................. 186
6.1 MSP430X CPU (CPUX) Introduction................................................................................... 187
6.2 Interrupts................................................................................................................... 189
6.3 CPU Registers ............................................................................................................ 190
6.3.1 Program Counter (PC) .......................................................................................... 190
6.3.2 Stack Pointer (SP) ............................................................................................... 190
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6.3.3 Status Register (SR) ............................................................................................ 192
6.3.4 Constant Generator Registers (CG1 and CG2) ............................................................. 193
6.3.5 General-Purpose Registers (R4 to R15)...................................................................... 194
6.4 Addressing Modes........................................................................................................ 196
6.4.1 Register Mode.................................................................................................... 197
6.4.2 Indexed Mode .................................................................................................... 198
6.4.3 Symbolic Mode................................................................................................... 203
6.4.4 Absolute Mode ................................................................................................... 207
6.4.5 Indirect Register Mode .......................................................................................... 209
6.4.6 Indirect Autoincrement Mode................................................................................... 210
6.4.7 Immediate Mode ................................................................................................. 211
6.5 MSP430 and MSP430X Instructions ................................................................................... 213
6.5.1 MSP430 Instructions ............................................................................................ 213
6.5.2 MSP430X Extended Instructions .............................................................................. 218
6.6 Instruction Set Description............................................................................................... 229
6.6.1 Extended Instruction Binary Descriptions..................................................................... 230
6.6.2 MSP430 Instructions ............................................................................................ 232
6.6.3 Extended Instructions ........................................................................................... 284
6.6.4 Address Instructions............................................................................................. 327
7 Flash Memory Controller ................................................................................................... 342
7.1 Flash Memory Introduction .............................................................................................. 343
7.2 Flash Memory Segmentation............................................................................................ 344
7.2.1 Segment A........................................................................................................ 345
7.3 Flash Memory Operation ................................................................................................ 346
7.3.1 Erasing Flash Memory .......................................................................................... 346
7.3.2 Writing Flash Memory ........................................................................................... 350
7.3.3 Flash Memory Access During Write or Erase................................................................ 357
7.3.4 Stopping Write or Erase Cycle................................................................................. 358
7.3.5 Checking Flash Memory ........................................................................................ 358
7.3.6 Configuring and Accessing the Flash Memory Controller .................................................. 359
7.3.7 Flash Memory Controller Interrupts ........................................................................... 359
7.3.8 Programming Flash Memory Devices......................................................................... 360
7.4 FCTL Registers ........................................................................................................... 361
7.4.1 FCTL1 Register .................................................................................................. 362
7.4.2 FCTL3 Register .................................................................................................. 363
7.4.3 FCTL4 Register .................................................................................................. 364
7.4.4 SFRIE1 Register ................................................................................................. 365
8 Memory Integrity Detection (MID)........................................................................................ 366
8.1 MID Overview ............................................................................................................. 367
8.2 Flash Memory With MID Support....................................................................................... 368
8.3 MID Parity Check Logic.................................................................................................. 368
8.4 Detecting Unprogrammed Memory Accesses ........................................................................ 369
8.5 MID ROM .................................................................................................................. 369
8.6 MID Support Software Function ........................................................................................ 369
8.6.1 MidEnable() Function............................................................................................ 370
8.6.2 MidDisable() Function ........................................................................................... 371
8.6.3 MidGetErrAdr() Function........................................................................................ 371
8.6.4 MidCheckMem() Function ...................................................................................... 372
8.6.5 MidSetRaw() Function........................................................................................... 372
8.6.6 MidGetParity() Function......................................................................................... 373
8.6.7 MidCalcVParity() Function...................................................................................... 373
8.7 User's UNMI Interrupt Handler.......................................................................................... 373
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SLAU208O–June 2008–Revised May 2015 Contents
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