/*
* CLOCK.c
*
* Created on: 2015年2月1日
* Author: sptj
* =user guide
*/
#include"MSP430F5438_CLOCK.h"
void CLOCK_Initial()
{
P7SEL|=BIT0+BIT1; //XT1 PORT LOW FREQUENCY 32768Hz
UCSCTL6&=~(XT1BYPASS+XT1OFF);
UCSCTL6 |= XCAP_3; // Internal load cap
P5SEL|=BIT2+BIT3;
UCSCTL6&=~(XT2BYPASS+XT2OFF); //XT2 PORT HIGH FREQUENCY 16MHz
do // Loop until XT1,XT2 & DCO stabilizes
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG); // Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
}while (SFRIFG1&OFIFG); // Test oscillator fault flag
UCSCTL6 &= ~(XT1DRIVE_3); // Xtal is now stable, reduce drive
UCSCTL6 &= ~XT2DRIVE0; // Decrease XT2 Drive according to expected frequency
UCSCTL6|=SMCLKOFF; //turn off the SMCLK
UCSCTL4|= SELA__XT1CLK | //ACLK->XT1
SELS__XT2CLK | //SMCLK->XT2
SELM__XT2CLK ; //MCLK->XT2
UCSCTL5|= DIVA__1 | //DEVIDER ACLK->1
DIVS__2 | //DEVIDER SMCLK->2
DIVM__2 ; //DEVIDER MCLK->2
/**************************************CLOCK OUTPUT*******************************************/
// P11DIR |= BIT0; // P11.0(84) to output direction
// P11SEL |= BIT0; // P11.0(84) to output ACLK
//
// P11DIR |= BIT1; // P11.1(85) to output direction
// P11SEL |= BIT1; // P11.1(85) to output MCLK
//
// P11DIR |= BIT2; // P11.2(86) to output direction
// P11SEL |= BIT2; // P11.2(86) to output SMCLK
/********************************************************************************************/
}
