Copyright © 2011 - 2015 Accellera. All rights reserved.
Universal Verification Methodology
(UVM) 1.2 User’s Guide
October 8, 2015
ii Copyright © 2011 - 2015 Accellera. All rights reserved.
October 8, 2015 UVM 1.2 User’s Guide
Copyright
©
2011 - 2015 Accellera Systems Initiative (Accellera). All rights reserved.
Accellera Systems Initiative, 8698 Elk Grove Bldv Suite 1, #114, Elk Grove, CA 95624, USA
Copyright
©
2013 - 2015 Advanced Micro Devices, Inc. All rights reserved.
Advanced Micro Devices (AMD), 7171 Southwest Parkway, Austin, TX 78735
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2011 - 2015 Cadence Design Systems, Inc. (Cadence). All rights reserved.
Cadence Design Systems, Inc., 2655 Seely Ave., San Jose, CA 95134, USA.
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2011 - 2015 Mentor Graphics, Corp. (Mentor). All rights reserved.
Mentor Graphics, Corp., 8005 SW Boeckman Rd., Wilsonville, OR 97070, USA
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2013 - 2015 NVIDIA CORPORATION. All rights reserved.
NVIDIA Corporation, 2701 San Tomas Expy, Santa Clara, CA 95050
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©
2011 - 2015 Synopsys, Inc. (Synopsys). All rights reserved.
Synopsys, Inc., 690 E. Middlefield Rd, Mountain View, CA 94043
This product is licensed under the Apache Software Foundation’s Apache License, Version 2.0,
January 2004. The full license is available at: http://www.apache.org/licenses/
.
Notices
While this guide offers a set of instructions to perform one or more specific verification tasks, it should be
supplemented by education, experience, and professional judgment. Not all aspects of this guide may be
applicable in all circumstances. The UVM 1.2 User’s Guide does not necessarily represent the standard of
care by which the adequacy of a given professional service must be judged nor should this document be
applied without consideration of a project’s unique aspects. This guide has been approved through the
Accellera consensus process and serves to increase the awareness of information and approaches in
verification methodology. This guide may have several recommendations to accomplish the same thing and
may require some judgment to determine the best course of action.
The UVM 1.2 Class Reference represents the foundation used to create the UVM 1.2 User’s Guide. This
guide is a way to apply the UVM 1.2 Class Reference, but is not the only way. Accellera believes standards
are an important ingredient to foster innovation and continues to encourage industry innovation based on its
standards.
Suggestions for improvements to the UVM 1.2 User’s Guide are welcome. They should be sent to the UVM
email reflector
uvm-wg@lists.accellera.org
Copyright © 2011 - 2015 Accellera. All rights reserved. iii
UVM 1.2 User’s Guide October 8, 2015
Contents
1. Overview.............................................................................................................................................. 1
1.1 The Typical UVM Testbench Architecture................................................................................ 1
1.1.1 UVM Testbench .......................................................................................................... 2
1.1.2 UVM Test ................................................................................................................... 2
1.1.3 UVM Environment ..................................................................................................... 2
1.1.4 UVM Scoreboard ........................................................................................................ 2
1.1.5 UVM Agent ................................................................................................................2
1.1.6 UVM Sequencer ......................................................................................................... 3
1.1.7 UVM Sequence ........................................................................................................... 3
1.1.8 UVM Driver ................................................................................................................ 3
1.1.9 UVM Monitor ............................................................................................................. 4
1.2 The UVM Class Library............................................................................................................. 4
2. Transaction-Level Modeling (TLM) ................................................................................................... 7
2.1 Overview .................................................................................................................................... 7
2.2 TLM, TLM-1, and TLM-2.0 ...................................................................................................... 7
2.3 TLM-1 Implementation.............................................................................................................. 8
2.3.1 Basics .......................................................................................................................... 8
2.3.2 Encapsulation and Hierarchy .................................................................................... 12
2.3.3 Analysis Communication .......................................................................................... 14
2.4 TLM-2.0 Implementation......................................................................................................... 16
2.4.1 Generic Payload ........................................................................................................ 16
2.4.2 Core Interfaces and Ports .......................................................................................... 19
2.4.3 Blocking Transport ................................................................................................... 20
2.4.4 Nonblocking Transport ............................................................................................. 20
2.4.5 Sockets ...................................................................................................................... 22
2.4.6 Time .......................................................................................................................... 25
2.4.7 Use Models ...............................................................................................................27
3. Developing Reusable Verification Components................................................................................ 29
3.1 Modeling Data Items for Generation ....................................................................................... 29
3.1.1 Inheritance and Constraint Layering ......................................................................... 30
3.1.2 Defining Control Fields (“Knobs”) ........................................................................... 31
3.2 Transaction-Level Components ............................................................................................... 32
3.3 Creating the Driver................................................................................................................... 34
3.4 Creating the Sequencer............................................................................................................. 35
3.5 Connecting the Driver and Sequencer..................................................................................... 35
3.5.1 Basic Sequencer and Driver Interaction ................................................................... 36
3.5.2 Querying for the Randomized Item .........................
................................................. 36
3.5.3 Fetching Consecutive Randomized Items ................................................................. 37
3.5.4 Sending Processed Data back to the Sequencer ........................................................ 37
3.5.5 Using TLM-Based Drivers ....................................................................................... 38
3.6 Creating the Monitor ................................................................................................................ 38
3.7 Instantiating Components......................................................................................................... 40
3.8 Creating the Agent ................................................................................................................... 41
3.8.1 Operating Modes ....................................................................................................... 41
3.8.2 Connecting Components ........................................................................................... 43
iv Copyright © 2011 - 2015 Accellera. All rights reserved.
October 8, 2015 UVM 1.2 User’s Guide
3.9 Creating the Environment ........................................................................................................ 43
3.9.1 The Environment Class ............................................................................................. 43
3.9.2 Invoking build_phase ................................................................................................ 44
3.10 Enabling Scenario Creation...................................................................................................... 44
3.10.1 Declaring User-Defined Sequences .......................................................................... 45
3.10.2 Sending Subsequences and Sequence Items ............................................................. 45
3.10.3 Starting a Sequence on a Sequencer ......................................................................... 48
3.10.4 Overriding Sequence Items and Sequences .............................................................. 49
3.11 Managing End of Test.............................................................................................................. 50
3.12 Implementing Checks and Coverage........................................................................................ 52
3.12.1 Implementing Checks and Coverage in Classes ....................................................... 52
3.12.2 Implementing Checks and Coverage in Interfaces ................................................... 54
3.12.3 Controlling Checks and Coverage ............................................................................ 54
4. Using Verification Components ........................................................................................................ 55
4.1 Creating a Top-Level Environment.......................................................................................... 55
4.2 Instantiating Verification Components .................................................................................... 56
4.3 Creating Test Classes ............................................................................................................... 58
4.4 Verification Component Configuration ................................................................................... 58
4.4.1 Verification Component Configurable Parameters ................................................... 58
4.4.2 Verification Component Configuration Mechanism ................................................ 59
4.4.3 Choosing between uvm_resource_db and uvm_config_db ...................................... 60
4.4.4 Using a Configuration Class ..................................................................................... 60
4.5 Creating and Selecting a User-Defined Test ............................................................................ 61
4.5.1 Creating the Base Test .............................................................................................. 61
4.5.2 Creating Tests from a Test-Family Base Class ......................................................... 61
4.5.3 Test Selection ............................................................................................................ 62
4.6 Creating Meaningful Tests....................................................................................................... 63
4.6.1 Constraining Data Items ........................................................................................... 63
4.6.2 Data Item Definitions ................................................................................................ 64
4.6.3 Creating a Test-Specific Frame ................................................................................ 64
4.7 Virtual Sequences..................................................................................................................... 65
4.7.1 Creating a Virtual Sequencer .................................................................................... 66
4.7.2 Creating a Virtual Sequence ..................................................................................... 67
4.7.3 Controlling Other Sequencers ................................................................................... 68
4.7.4 Connecting a Virtual Sequencer to Subsequencers .................................................. 69
4.8 Checking for DUT Correctness................................................................................................70
4.9 Scoreboards .................................................
............................................................................. 70
4.9.1 Creating the Scoreboard ............................................................................................ 71
4.9.2 Adding Exports to uvm_scoreboard ......................................................................... 71
4.9.3 Requirements of the TLM Implementation .............................................................. 72
4.9.4 Defining the Action Taken ....................................................................................... 72
4.9.5 Adding the Scoreboard to the Environment ............................................................. 72
4.9.6 Summary ................................................................................................................... 73
4.10 Implementing a Coverage Model............................................................................................. 73
4.10.1 Selecting a Coverage Method ................................................................................... 73
4.10.2 Implementing a Functional Coverage Model ........................................................... 74
4.10.3 Enabling and Disabling Coverage ............................................................................ 74
5. Using the Register Layer Classes ...................................................................................................... 75
5.1 Overview .................................................................................................................................. 75
5.2 Usage Model ............................................................................................................................ 75
Copyright © 2011 - 2015 Accellera. All rights reserved. v
UVM 1.2 User’s Guide October 8, 2015
5.2.1 Sub-register Access ................................................................................................... 78
5.2.2 Mirroring ................................................................................................................... 79
5.2.3 Memories are not Mirrored ....................................................................................... 80
5.3 Access API ............................................................................................................................... 80
5.3.1 read / write ................................................................................................................ 80
5.3.2 peek / poke ................................................................................................................ 81
5.3.3 get / set ...................................................................................................................... 81
5.3.4 randomize .................................................................................................................. 81
5.3.5 update ........................................................................................................................ 82
5.3.6 mirror ........................................................................................................................ 82
5.3.7 Concurrent Accesses ................................................................................................. 82
5.4 Coverage Models...................................................................................................................... 83
5.4.1 Predefined Coverage Identifiers ............................................................................... 83
5.4.2 Controlling Coverage Model Construction and Sampling ....................................... 83
5.5 Constructing a Register Model................................................................................................. 84
5.5.1 Field Types ............................................................................................................... 84
5.5.2 Register Types .......................................................................................................... 90
5.5.3 Register File Types ................................................................................................... 93
5.5.4 Memory Types .......................................................................................................... 95
5.5.5 Block Types ..............................................................................................................96
5.5.6 Packaging a Register Model ................................................................................... 100
5.5.7 Maximum Data Size ............................................................................................... 100
5.6 Back-door Access................................................................................................................... 101
5.6.1 Back-door read/write vs. peek/poke ....................................................................... 101
5.6.2 Hierarchical HDL Paths .......................................................................................... 102
5.6.3 VPI-based Back-door Access ................................................................................. 103
5.6.4 User-defined Back-door Access ............................................................................. 104
5.6.5 Back-door Access for Protected Memories ............................................................ 104
5.6.6 Active Monitoring ................................................................................................... 105
5.7 Special Registers .................................................................................................................... 106
5.7.1 Pre-defined Special Registers ................................................................................. 107
5.7.2 Unmapped Registers and Memories ....................................................................... 108
5.7.3 Aliased Registers .................................................................................................... 110
5.7.4 Unimplemented Registers ....................................................................................... 112
5.7.5 RO and WO Registers Sharing the Same Address ................................................. 113
5.8 Integrating a Register Model in a Verification Environment................................................. 114
5.9 Integrating a Register Model...............................................................................................
... 114
5.9.1 Transaction Adapter ................................................................................................ 115
5.9.2 Integrating Bus Sequencers .................................................................................... 117
5.9.3 Integrating the Register Model with a Bus Monitor ............................................... 123
5.10 Randomizing Field Values..................................................................................................... 125
5.11 Pre-defined Sequences ........................................................................................................... 125
6. Advanced Topics ............................................................................................................................. 129
6.1 The uvm_component Base Class ........................................................................................... 129
6.2 The Built-In Factory and Overrides ....................................................................................... 129
6.2.1 About the Factory ................................................................................................... 129
6.2.2 Factory Registration ................................................................................................ 130
6.2.3 Component Overrides ............................................................................................. 130
6.3 Callbacks ................................................................................................................................ 133
6.3.1 Use Model ............................................................................................................... 133
6.3.2 Example ..................................................................................................................134
6.4 The Sequence Library ............................................................................................................ 137
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