2018.3:
* Version 8.4 (Rev. 2)
* Feature Enhancement: Read Latency Support added for URAM when selected through IP Integrator
* Other: Power Calculations disabled for URAM primitives in IP GUI, no functional changes
* Other: Internal device family change, no functional changes
2018.2:
* Version 8.4 (Rev. 1)
* No changes
2018.1:
* Version 8.4 (Rev. 1)
* No changes
2017.4:
* Version 8.4 (Rev. 1)
* General: Write depth shown in IP GUI is now dependent on number of BRAMs available in a chosen device, no functional changes
2017.3:
* Version 8.4
* General: Safety Circuit option is enabled by default if reset option in any one port is enabled
2017.2:
* Version 8.3 (Rev. 6)
* No changes
2017.1:
* Version 8.3 (Rev. 6)
* General: Internal device family change, no functional changes
* General: When common_clock is selected clkb is internally connected to clka, but the interface remains same to support the backword compatiability. User make sure of connecting the both the clocks to same clock source when in common_clock mode
2016.4:
* Version 8.3 (Rev. 5)
* General: Fixes for behavioral Model issues when built-IN ECC is enabled (to be consistent with RTL)
2016.3:
* Version 8.3 (Rev. 4)
* Feature Enhancement: URAM addressing updates while calling XPM_Memory when 32-bit addressing is enabled
* Other: Enable support for future devices
* Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user
2016.2:
* Version 8.3 (Rev. 3)
* updated the IP,not to set WRITE_DEPTH parameter to 8192 everytime when the mode is switched to BRAM_Controller
* Updated the IP to support the device package changes
2016.1:
* Version 8.3 (Rev. 2)
* Updated the IP to deliver only verilog behavioral model
* Updated the IP to support UltraRAM in IP Integrator
* Updated the IP to support the device package changes
2015.4.2:
* Version 8.3 (Rev. 1)
* No changes
2015.4.1:
* Version 8.3 (Rev. 1)
* No changes
2015.4:
* Version 8.3 (Rev. 1)
* Updated the IP to support the device package changes
2015.3:
* Version 8.3
* IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
* New ports rsta_busy and rstb_busy are added to enable the safety circuitry to minimize the occurrence of BRAM data corruption
* Simulation models are delivered in VHDL only
2015.2.1:
* Version 8.2 (Rev. 5)
* No changes
2015.2:
* Version 8.2 (Rev. 5)
* No changes
2015.1:
* Version 8.2 (Rev. 5)
* Delivering non encrypted behavioral models
* Supported memory depth is increased up to 1M words
* Added the power saving feature (RDADDRCHG) for ultrascale devices
* Supported devices and production status are now determined automatically, to simplify support for future devices
2014.4.1:
* Version 8.2 (Rev. 4)
* Updated the IP to support the device package changes
2014.4:
* Version 8.2 (Rev. 3)
* Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
* Added support for 7-series Automotive (XA) and Defense Grade (XQ) devices
* Internal device family change, no functional changes
2014.3:
* Version 8.2 (Rev. 2)
* Fixed the Memory Resource Doubling issue in Simple Dual Port RAM when aspect ratio is used
* Fixed the GUI crash in Simple Dual Port RAM
* Added support of all write modes in Simple Dual Port RAM when ECC is not used
* Increased the supported depth to a maximum value of 256k
2014.2:
* Version 8.2 (Rev. 1)
* Updated the GUI tool tip for Byte write enable in the page-1 of block memory generator GUI
2014.1:
* Version 8.2
* Added support of the cascaded Primitives of widths 1 and 2 for ultra-scale devices
* Added support of the ECCPIPE register in the built-in ecc mode for ultra-scale devices
* Added support of the dynamic power saving for ultra-scale devices
* Improved timing efficiency in the IP Integrator by minimizing the use of output mux for the 7-series devices
* Internal device family name change, no functional changes
2013.4:
* Version 8.1
* The Primitive output registers are made "ON" by default in the stand alone mode
* Added cascaded support for ultrascale devices to construct 64Kx1 primitive by using two 32Kx1 primitives
* Added support for ultrascale devices
2013.3:
* Version 8.0 (Rev. 2)
* Added parameter "CTRL_ECC_ALGO" for supporting ECC in IP Integrator.
* Improved GUI speed and responsivness, no functional changes
* Reduced synthesis and simulation warnings
* Added support for Cadence IES and Synopsys VCS simulators
* Changed the default option of ENABLE PORT TYPE to "USE_ENA_PIN"
* Changed BRAM Interface DIN and DOUT to match bus interface directions.
2013.2:
* Version 8.0 (Rev. 1)
* No Changes
2013.1:
* Version 8.0
* Native Vivado Release
* There have been no functional or interface changes to this IP. The version number has changed to support unique versioning in Vivado starting with 2013.1.
(c) Copyright 2002 - 2018 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
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xilinx在线升级.zip (46个子文件)
xilinx在线升级
updata
fpga_spi.xdc 1KB
update_spi
update_spi_drive.v 13KB
icap_start.v 6KB
update_spi_control.v 16KB
ip
.Xil
.cor_data_to_flash.xcix.lock 0B
updata_spi_flash_bram
updata_spi_flash_bram_ooc.xdc 3KB
misc
blk_mem_gen_v8_4.vhd 8KB
hdl
blk_mem_gen_v8_4_vhsyn_rfs.vhd 14.18MB
updata_spi_flash_bram_sim_netlist.vhdl 50KB
updata_spi_flash_bram_stub.vhdl 2KB
updata_spi_flash_bram.veo 3KB
updata_spi_flash_bram_stub.v 1KB
updata_spi_flash_bram.vho 3KB
updata_spi_flash_bram.xci 39KB
sim
updata_spi_flash_bram.v 7KB
updata_spi_flash_bram_sim_netlist.v 36KB
updata_spi_flash_bram.dcp 35KB
doc
blk_mem_gen_v8_4_changelog.txt 7KB
summary.log 983B
simulation
blk_mem_gen_v8_4.v 167KB
synth
updata_spi_flash_bram.vhd 15KB
updata_spi_flash_bram.xml 227KB
update_spi_wrap.v 15KB
golden
fpga_spi.xdc 1KB
update_spi
update_spi_drive.v 13KB
icap_start.v 6KB
update_spi_control.v 16KB
ip
.Xil
.cor_data_to_flash.xcix.lock 0B
updata_spi_flash_bram
updata_spi_flash_bram_ooc.xdc 3KB
misc
blk_mem_gen_v8_4.vhd 8KB
hdl
blk_mem_gen_v8_4_vhsyn_rfs.vhd 14.18MB
updata_spi_flash_bram_sim_netlist.vhdl 50KB
updata_spi_flash_bram_stub.vhdl 2KB
updata_spi_flash_bram.veo 3KB
updata_spi_flash_bram_stub.v 1KB
updata_spi_flash_bram.vho 3KB
updata_spi_flash_bram.xci 39KB
sim
updata_spi_flash_bram.v 7KB
updata_spi_flash_bram_sim_netlist.v 36KB
updata_spi_flash_bram.dcp 35KB
doc
blk_mem_gen_v8_4_changelog.txt 7KB
summary.log 983B
simulation
blk_mem_gen_v8_4.v 167KB
synth
updata_spi_flash_bram.vhd 15KB
updata_spi_flash_bram.xml 227KB
update_spi_wrap.v 15KB
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