formal:体验Verilog和VHDL的形式验证
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2021-05-21
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formal:体验Verilog和VHDL的形式验证 （117个子文件） 
prog.asm 176KB prog_simple.asm 986B tb_cpu.gtkw 54KB rubik_sim.gtkw 4KB rubik_sim.gtkw 3KB fetch.gtkw 2KB memory.gtkw 2KB fetch.gtkw 1KB two_stage_buffer.gtkw 1KB wb_tdp_mem.gtkw 1KB one_stage_buffer.gtkw 983B one_stage_fifo.gtkw 971B rubik.gtkw 945B two_stage_fifo.gtkw 943B wb_mem.gtkw 864B pipe_concat.gtkw 809B rubik.gtkw 787B fgc.gtkw 714B LICENSE 1KB Makefile 2KB Makefile 1KB Makefile 996B Makefile 985B Makefile 957B Makefile 948B Makefile 946B Makefile 946B Makefile 862B Makefile 862B Makefile 669B Makefile 668B Makefile 664B Makefile 202B README.md 11KB README.md 10KB README.md 8KB README.md 6KB README.md 5KB README.md 4KB README.md 3KB INSTALL.md 3KB README.md 2KB README.md 2KB README.md 2KB README.md 1KB README.md 1KB README.md 287B README.md 240B README.md 52B
waveform.png 78KB waveform.png 74KB waveform.png 74KB twisted.png 47KB swapped.png 47KB waveform.png 46KB waveform.png 42KB waveform.png 41KB cover_statement.png 28KB waveform.png 28KB cover_statement.png 27KB waveform.png 25KB cpu.png 23KB fetch.psl 9KB fetch.psl 7KB memory.psl 7KB rubik.psl 4KB one_stage_buffer.psl 3KB two_stage_buffer.psl 3KB rubik.psl 3KB one_stage_fifo.psl 3KB wb_tdp_mem.psl 2KB wb_mem.psl 2KB two_stage_fifo.psl 2KB pipe_concat.psl 2KB fgc.psl 793B fetch.sby 819B two_stage_buffer.sby 435B memory.sby 332B wb_tdp_mem.sby 295B fetch.sby 278B pipe_concat.sby 266B one_stage_buffer.sby 265B one_stage_fifo.sby 253B two_stage_fifo.sby 253B wb_mem.sby 247B rubik.sby 246B rubik.sby 207B fgc.sby 135B decode.vhd 18KB cpu_constants.vhd 10KB cpu.vhd 10KB execute.vhd 9KB rubik.vhd 8KB rubik.vhd 7KB fetch.vhd 5KB fetch.vhd 5KB memory.vhd 4KB registers.vhd 4KB alu_flags.vhd 4KB alu_data.vhd 4KB共 117 条
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