对verilog编写的HDL模块的功能验证

If you survey hardware design groups, you will learn that between 60 and 80 percent of their effort is now dedicated to verification. Unlike synthesizeable coding, there is no particular coding style required for verification. The freedom of using any features of the languages has produced a wide array of techniques and approaches to verification. The absence of constraints and lack of available ad hoc expertise and references in verification has resulted in approaches. The consequences of an informal verification process can range from a non-functional design requiring several re-spins, through a design with only a subset of the intended functionality, to a delayed product shipment.