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DE10-Nano_User_manual
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DE10-Nano_User_manual.很好的一款FPGA开发板,供大家学习
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DE10-Nano
User Manual
1
www.terasic.com
March 31, 2017
Chapter 1 DE10-Nano Development Kit 3
1.1 Package Contents 3
1.2 DE10-Nano System CD 4
1.3 Getting Help 4
Chapter 2 Introduction of the DE10-Nano Board 5
2.1 Layout and Components 5
2.2 Block Diagram of the DE10-Nano Board 8
Chapter 3 Using the DE10-Nano Board 11
3.1 Settings of FPGA Configuration Mode 11
3.2 Configuration of Cyclone V SoC FPGA on DE10-Nano 13
3.3 Board Status Elements 20
3.4 Board Reset Elements 21
3.5 Clock Circuitry 22
3.6 Peripherals Connected to the FPGA 24
3.6.1 User Push-buttons, Switches and LEDs 24
3.6.2 2x20 GPIO Expansion Headers 27
3.6.3 Arduino Uno R3 Expansion Header 30
3.6.4 A/D Converter and Analog Input 32
3.6.5 HDMI TX Interface 34
3.7 Peripherals Connected to Hard Processor System (HPS) 36
3.7.1 User Push-buttons and LEDs 36
3.7.2 Gigabit Ethernet 36
3.7.3 UART 38
3.7.4 DDR3 Memory 39
3.7.5 Micro SD Card Socket 42
3.7.6 USB 2.0 OTG PHY 43
3.7.7 G-sensor 44
3.7.8 LTC Connector 45
Chapter 4 DE10-Nano System Builder 46
4.1 Introduction 46
4.2 Design Flow 47
4.3 Using DE10-Nano System Builder 48
DE10-Nano
User Manual
2
www.terasic.com
March 31, 2017
Chapter 5 Examples For FPGA 54
5.1 DE10-Nano Factory Configuration 54
5.2 ADC Reading 55
5.3 HDMI TX 58
5.4 DDR3_VIP 62
5.5 DDR3_RTL 68
5.6 Nios II Access HPS DDR3 73
Chapter 6 Examples for HPS SoC 78
6.1 Hello Program 78
6.2 Users LED and KEY 81
6.3 I2C Interfaced G-sensor 88
6.4 Setup USB Wi-Fi Dongle 91
6.5 Query Internet Time 94
Chapter 7 Examples for using both HPS SoC and FGPA 96
7.1 Required Background 96
7.2 System Requirements 97
7.3 AXI bridges in Intel SoC FPGA 97
7.4 GHRD Project 99
7.5 Compile and Programming 100
7.6 Develop the C Code 101
Chapter 8 Programming the EPCS Device 107
8.1 Before Programming Begins 107
8.2 Convert .SOF File to .JIC File 108
8.3 Write JIC File into the EPCS Device 113
8.4 Erase the EPCS Device 115
8.5 EPCS Programming via nios-2-flash-programmer 116
Chapter 9 Appendix A 117
9.1 Revision History 117
DE10-Nano
User Manual
3
www.terasic.com
March 31, 2017
Chapter 1
DE10-Nano
Development Kit
he DE10-Nano Development Kit presents a robust hardware design platform built
around the Intel System-on-Chip (SoC) FPGA, which combines the latest dual-core
Cortex-A9 embedded cores with industry-leading programmable logic for ultimate
design flexibility. Users can now leverage the power of tremendous re-configurability paired
with a high-performance, low-power processor system. Intel’s SoC integrates an
ARM-based hard processor system (HPS) consisting of processor, peripherals and
memory interfaces tied seamlessly with the FPGA fabric using a high-bandwidth
interconnect backbone. The DE10-Nano development board is equipped with high-speed
DDR3 memory, analog to digital capabilities, Ethernet networking, and much more that
promise many exciting applications.
The DE10-Nano Development Kit contains all the tools needed to use the board in
conjunction with a computer that runs the Microsoft Windows XP or later.
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Figure 1-1 shows a photograph of the DE10-Nano package.
Figure 1-1 The DE10-Nano package contents
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DE10-Nano
User Manual
4
www.terasic.com
March 31, 2017
The DE10-Nano package includes:
The DE10-Nano development board
DE10-Nano Quick Start Guide
USB cable Type A to Mini-B for FPGA programming or UART control
USB cable Type A to Micro-B for USB OTG connect to PC
5V DC power adapter
microSD Card (Installed)
Four Silicon Footstands
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The DE10-Nano System CD contains all the documents and supporting materials
associated with DE10-Nano, including the user manual, system builder, reference designs,
and device datasheets. Users can download this system CD from the link:
http://de10-nano.terasic.com/cd.
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Here are the addresses where you can get help if you encounter any problems:
Terasic Technologies
9F., No.176, Sec.2, Gongdao 5th Rd, East Dist, Hsinchu City, 30070. Taiwan
Email: support@terasic.com
Tel.: +886-3-575-0880
Website: DE10-Nano.terasic.com
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