de0-nano-soc_5CSEMA4U23C6N 开发板原理图

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D D

C C

B B

A A

ALTERA Cyclone V SoC Development & Education Board (DE1-SoC)

CONTENT

1 Cover Page

8

9

Block Diagram

FPGA BANK 3, BANK 4

FPGA BANK 5, BANK 6

JTAG Chain

GPIO 0

GPIO 1

SDRAM, HPS QSPI Flash

HPS DDR3 SDRAM15

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

All rights reserved.

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

All rights reserved.

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

All rights reserved.

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5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

All rights reserved.

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

All rights reserved.

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

All rights reserved.

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4

4

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2

2

1

1

D D

C C

B B

A A

VCCIO = 3.3V

VCCIO = 3.3V

USB_B2_DATA1

USB_B2_DATA2

USB_B2_DATA3

USB_B2_DATA4

USB_B2_DATA6

USB_B2_DATA7

GPIO_028

GPIO_029

GPIO_124

GPIO_122

GPIO_120

GPIO_131

GPIO_019

GPIO_024

GPIO_117

GPIO_118

GPIO_19

GPIO_119

GPIO_132

GPIO_15

LEDR3

LEDR5

GPIO_113

GPIO_116

GPIO_115

LEDR6

GPIO_112

GPIO_17

GPIO_18

GPIO_135

GPIO_13

GPIO_11

GPIO_12

SW5

DRAM_DQ5

DRAM_DQ11

GPIO_0[35..0]

6,12

GPIO_1[35..0]

6,13

SW[9..0] 7,20

LEDR[9..0]

4,19

FAN_CTRL 7

DRAM_CAS_N14

DRAM_BA014

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

All rights reserved.

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

All rights reserved.

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

All rights reserved.

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4

4

3

3

2

2

1

1

D D

C C

B B

A A

VCCIO = 1.5V

VCCIO = 1.5V

VCCIO = 3.3V

VCCIO = 3.3V

HPS_DDR3_DQ16

HPS_DDR3_DQ17

HPS_DDR3_DQ20

HPS_DDR3_DQ21

HPS_DDR3_DQ22

HPS_DDR3_DQ23

HPS_DDR3_DQS_P2

HPS_DDR3_DQS_N2

HPS_DDR3_DQ13

HPS_DDR3_DQ14

HPS_DDR3_DQ15

HPS_DDR3_DQS_P1

HPS_DDR3_DQS_N1

HPS_DDR3_DQ0

HPS_DDR3_DQ4

HPS_DDR3_DQ5

HPS_DDR3_DQ6

HPS_DDR3_DQ7

HPS_DDR3_DM0

HPS_DDR3_DQS_P0

HPS_DDR3_DQS_N0

HPS_DDR3_CKE15

HPS_DDR3_ODT15

LEDR[9..0]

6,19

7,19

19

6,19

21

HPS_DDR3_DQS_N[3..0] 15

HPS_DDR3_DQS_P[3..0] 15

HPS_DDR3_DQ[31..0] 15

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

All rights reserved.

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

All rights reserved.

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

All rights reserved.

Y28

V29

U20

T21

U28

P29

N30

L29

L30

K28

H29

N18

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VCCIO = 3.3V

VCCIO = 3.3V

VCCIO = 3.3V

(BOOTSEL0)

(BOOTSEL1)

(BOOTSEL2)

(CLOCKSEL0)

HPS_CLOCK1_25

HPS_CLOCK2_25

HPS_CLK_25

VGA_B3

VGA_G5

VGA_G1

VGA_G0

TD_DATA7

TD_DATA6

TD_DATA5

TD_DATA4

TD_DATA3

TD_DATA2

TD_DATA1

TD_DATA0

VCC3P3

VCC3P3

HPS_SPIM_SS

HPS_LED26

HPS_KEY26

HPS_I2C1_SCLK

HPS_I2C1_SDAT

25,26

HPS_ENET_GTX_CLK 23

HPS_ENET_TX_EN 23

HPS_ENET_RX_CLK 23

HPS_ENET_RX_DATA[3..0]

23

14

HPS_SD_DATA0 24

HPS_LTC_GPIO 25

HPS_CONV_USB_N24

AUD_XCK18

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

All rights reserved.

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

All rights reserved.

Copyright (c) 2013 by Terasic Technologies Inc. Taiwan.

No part of this schematic design may be reproduced, duplicated, or used without the prior written permission of Terasic.

All rights reserved.

A23

C22

B23

C23

D22

E24

D24

A8

C7

B7