嵌入式物联网项目实战-STM32F103实现DMA直接内存访问功能串口DMA配置

; generated by ARM C/C++ Compiler, 4.1 [Build 481] ; commandline ArmCC [--debug -c --asm --interleave -o.\output\stm32f10x_tim.o --depend=.\output\stm32f10x_tim.d --cpu=Cortex-M3 --apcs=interwork -O0 -I.\lib\inc -I.\lib\src -IC:\Keil\ARM\INC -IC:\Keil\ARM\INC\ST\STM32F10x -D__MICROLIB --omf_browse=.\output\stm32f10x_tim.crf lib\src\stm32f10x_tim.c] THUMB AREA ||.text||, CODE, READONLY, ALIGN=2 TIM_DeInit PROC ;;;136 *******************************************************************************/ ;;;137 void TIM_DeInit(TIM_TypeDef* TIMx) 000000 b510 PUSH {r4,lr} ;;;138 { 000002 4604 MOV r4,r0 ;;;139 /* Check the parameters */ ;;;140 assert_param(IS_TIM_ALL_PERIPH(TIMx)); ;;;141 ;;;142 switch (*(u32*)&TIMx) 000004 49fc LDR r1,|L1.1016| 000006 1a60 SUBS r0,r4,r1 000008 428c CMP r4,r1 00000a d045 BEQ |L1.152| 00000c dc0c BGT |L1.40| 00000e f1b44f80 CMP r4,#0x40000000 000012 d01d BEQ |L1.80| 000014 48f9 LDR r0,|L1.1020| 000016 1820 ADDS r0,r4,r0 000018 d023 BEQ |L1.98| 00001a f5b06f80 CMP r0,#0x400 00001e d029 BEQ |L1.116| 000020 f5b06f00 CMP r0,#0x800 000024 d154 BNE |L1.208| 000026 e02e B |L1.134| |L1.40| 000028 f5b06f80 CMP r0,#0x400 00002c d03d BEQ |L1.170| 00002e f5b03f8e CMP r0,#0x11c00 000032 d003 BEQ |L1.60| 000034 f5b03f92 CMP r0,#0x12400 000038 d14a BNE |L1.208| 00003a e03f B |L1.188| |L1.60| ;;;143 { ;;;144 case TIM1_BASE: ;;;145 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); 00003c 2101 MOVS r1,#1 00003e 02c8 LSLS r0,r1,#11 000040 f7fffffe BL RCC_APB2PeriphResetCmd ;;;146 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); 000044 2100 MOVS r1,#0 000046 f44f6000 MOV r0,#0x800 00004a f7fffffe BL RCC_APB2PeriphResetCmd ;;;147 break; 00004e e040 B |L1.210| |L1.80| ;;;148 ;;;149 case TIM2_BASE: ;;;150 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); 000050 2101 MOVS r1,#1 000052 4608 MOV r0,r1 000054 f7fffffe BL RCC_APB1PeriphResetCmd ;;;151 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); 000058 2100 MOVS r1,#0 00005a 2001 MOVS r0,#1 00005c f7fffffe BL RCC_APB1PeriphResetCmd ;;;152 break; 000060 e037 B |L1.210| |L1.98| ;;;153 ;;;154 case TIM3_BASE: ;;;155 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); 000062 2101 MOVS r1,#1 000064 2002 MOVS r0,#2 000066 f7fffffe BL RCC_APB1PeriphResetCmd ;;;156 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); 00006a 2100 MOVS r1,#0 00006c 2002 MOVS r0,#2 00006e f7fffffe BL RCC_APB1PeriphResetCmd ;;;157 break; 000072 e02e B |L1.210| |L1.116| ;;;158 ;;;159 case TIM4_BASE: ;;;160 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); 000074 2101 MOVS r1,#1 000076 2004 MOVS r0,#4 000078 f7fffffe BL RCC_APB1PeriphResetCmd ;;;161 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); 00007c 2100 MOVS r1,#0 00007e 2004 MOVS r0,#4 000080 f7fffffe BL RCC_APB1PeriphResetCmd ;;;162 break; 000084 e025 B |L1.210| |L1.134| ;;;163 ;;;164 case TIM5_BASE: ;;;165 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE); 000086 2101 MOVS r1,#1 000088 2008 MOVS r0,#8 00008a f7fffffe BL RCC_APB1PeriphResetCmd ;;;166 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE); 00008e 2100 MOVS r1,#0 000090 2008 MOVS r0,#8 000092 f7fffffe BL RCC_APB1PeriphResetCmd ;;;167 break; 000096 e01c B |L1.210| |L1.152| ;;;168 ;;;169 case TIM6_BASE: ;;;170 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); 000098 2101 MOVS r1,#1 00009a 2010 MOVS r0,#0x10 00009c f7fffffe BL RCC_APB1PeriphResetCmd ;;;171 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); 0000a0 2100 MOVS r1,#0 0000a2 2010 MOVS r0,#0x10 0000a4 f7fffffe BL RCC_APB1PeriphResetCmd ;;;172 break; 0000a8 e013 B |L1.210| |L1.170| ;;;173 ;;;174 case TIM7_BASE: ;;;175 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); 0000aa 2101 MOVS r1,#1 0000ac 2020 MOVS r0,#0x20 0000ae f7fffffe BL RCC_APB1PeriphResetCmd ;;;176 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); 0000b2 2100 MOVS r1,#0 0000b4 2020 MOVS r0,#0x20 0000b6 f7fffffe BL RCC_APB1PeriphResetCmd ;;;177 break; 0000ba e00a B |L1.210| |L1.188| ;;;178 ;;;179 case TIM8_BASE: ;;;180 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); 0000bc 2101 MOVS r1,#1 0000be 0348 LSLS r0,r1,#13 0000c0 f7fffffe BL RCC_APB2PeriphResetCmd ;;;181 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE); 0000c4 2100 MOVS r1,#0 0000c6 f44f5000 MOV r0,#0x2000 0000ca f7fffffe BL RCC_APB2PeriphResetCmd ;;;182 break; 0000ce e000 B |L1.210| |L1.208| ;;;183 ;;;184 default: ;;;185 break; 0000d0 bf00 NOP |L1.210| 0000d2 bf00 NOP ;147 ;;;186 } ;;;187 } 0000d4 bd10 POP {r4,pc} ;;;188 ENDP TIM_TimeBaseInit PROC ;;;201 *******************************************************************************/ ;;;202 void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) 0000d6 8802 LDRH r2,[r0,#0] ;;;203 { ;;;204 /* Check the parameters */ ;;;205 assert_param(IS_TIM_123458_PERIPH(TIMx)); ;;;206 assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); ;;;207 assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision)); ;;;208 ;;;209 /* Select the Counter Mode and set the clock division */ ;;;210 TIMx->CR1 &= CR1_CKD_Mask & CR1_CounterMode_Mask; 0000d8 f002028f AND r2,r2,#0x8f 0000dc 8002 STRH r2,[r0,#0] ;;;211 TIMx->CR1 |= (u32)TIM_TimeBaseInitStruct->TIM_ClockDivision | 0000de 88ca LDRH r2,[r1,#6] 0000e0 884b LDRH r3,[r1,#2] 0000e2 431a ORRS r2,r2,r3 0000e4 8803 LDRH r3,[r0,#0] 0000e6 431a ORRS r2,r2,r3 0000e8 8002 STRH r2,[r0,#0