December 2009 Doc ID 16795 Rev 1 1/10
AN3109
Application note
Communication peripheral FIFO emulation with DMA
and DMA timeout in STM32F10x microcontrollers
Introduction
The STM32™ communication peripherals have a single transmit buffer and a single receive
buffer. The user software should therefore retrieve data from the receive buffer before the
data are overwritten by the next received data. With interrupts, there is a risk of data
overflow. The STM32’s DMA feature prevents data overflow but, usually, the number of data
items to be received is not known in advance, and it is variable (from one reception
sequence to the next). Consequently, in reception, the end of transfer cannot be detected.
The solution is to implement an emulated FIFO based on both DMA and interrupts, a DMA
timeout is required to indicated to the application that no further data will be received.
The only requirements for FIFO implementation are that the original data and their order are
preserved. Because it is so simple, FIFO structures are easily implemented in both
hardware and software.
This application note is based on the implementation of a simple 200-byte circular buffer, but
the principle can be extended to buffers of any size. Likewise, the peripheral used here is
the USART but the same principle can be adopted for any other communication peripheral.
The aim of this document is to show how to build an efficient circular FIFO using the
STM32F10x’s DMA, and to provide methods for the implementation of DMA timeout.
This application note is organized into two parts. It first gives a FIFO overview: it discusses
FIFO emulation in the STM32’s system RAM and provides a description of the software
required for FIFO implementation. Then it provides two methods for the implementation of
DMA timeout.
This application note assumes that the reader is familiar with the STM32’s DMA as
described in the STM32F10xx reference manual, RM0008, available for the
STMicroelectronics website www.st.com.
www.st.com
