matlab匹配滤波代码-EE332-FIR-Filter-Using-VHDL:使用VHDL的FIR滤波器

matlab匹配滤波代码 Issues and References ~~ synthesis error The problem is that, for synthesizing, Xilinx assumes every port is either of type std_logic or std_logic_vector (as it generates a new VHDL file that executed the synthesized model, including precise timing simulation). In order for it to work with a synthesizer, I should change the entity definition to std_logic_vector. change data to std_logic_vector change coefficient to constant in type package power too large issues 在constraint里写： creat