VHDL Example 2: LUT to Evaluate Partial Products for Four Taps
Entity PartialProd
c1 : std_logic_vector := “01001001”; -- coefficient for tap 1
c2 : std_logic_vector := “10010101”; -- coefficient for tap 2
c3 : std_logic_vector := “10010010”; -- coefficient for tap 3
c3 : std_logic_vector := “01101010”; -- coefficient for tap 4
Port ( D : std_logic_vector(3 downto 0);
P : std_logic_vector(9 downto 0)); -- 4 * 8 bit coeff => 10 bit product
End PartialProd;
Architecture Behave of PartialProd is
-- Compute all the partial products and store them as constants.
constant v0 : std_logic_vector := sxt(“0”, 10);
constant v1 : std_logic_vector := sxt(c1, 10);
constant v2 : std_logic_vector := sxt(c2, 10);
constant v3 : std_logic_vector := v1 + v2;
constant v4 : std_logic_vector := sxt(c3, 10);
constant v5 : std_logic_vector := v4 + v1;
constant v6 : std_logic_vector := v4 + v2;
constant v7 : std_logic_vector := v4 + v3;
constant v8 : std_logic_vector := sxt(c4, 10);
constant v9 : std_logic_vector := v8 + v1;
constant v10 : std_logic_vector := v8 + v2;
constant v11 : std_logic_vector := v8 + v3;
constant v12 : std_logic_vector := v8 + v4;
constant v13 : std_logic_vector := v8 + v5;
constant v14 : std_logic_vector := v8 + v6;
constant v15 : std_logic_vector := v8 + v7;
Begin
prodeval: process (D)
begin
case(d) is
when “0000” => P <= v0;
when “0001” => P <= v1;
when “0010” => P <= v2;
when “0011” => P <= v3;
when “0100” => P <= v4;
when “0101” => P <= v5;
when “0110” => P <= v6;
when “0111” => P <= v7;
when “1000” => P <= v8;
when “1001” => P <= v9;
when “1010” => P <= v10;
when “1011” => P <= v11;
when “1100” => P <= v12;
when “1101” => P <= v13;
when “1110” => P <= v14;
