安森美半导体ESD保护器件NUP4304M6-D 数据手册pdf,安森美半导体ESD保护器件NUP4304M6-D 数据手册
NUP4304MR6 Curves Applicable to Each Cathode 100 TA=150°C TA=125°C 10 10 TA=-40°C TA=85°C 01 1.0 To=25C =55°C c001 TA=25°C 0.1 0.001 04 0.8 10 2 VF, FORWARD VOLTAGE(VOLTS) VR, REVERSE VOLTAGE (VOLTS) Figure 1. Forward voltage Figure 2. Leakage Current 1.75 15 uzouo 1.25 10 0.75 VR, REVERSE VOLTAGE (VOLTS) Figure 3. Capacitance http://onsemi.co 3 NUP4304MR6 APPLICATIONS INFORMATION The NUP4304MR6 is a low capacitance diode array option 2 designed to protect sensitive electronics such as Protection of four data lines and the supply rail using vcc communications systems, computers, and computer as a reference and an external tvs diode peripherals against damage due to ESD events or transient lo 1 overvoltage conditions. Because of its low capacitance, it lo 2 can be used on high speed i o data lines The integrated design of the NUP4304MR6 offers surge rated, low capacitance steering diodes integrated in a single package (TSOP-6. If a transient condition occurs, the steering diodes will drive the transient to the positive rail of the power supply or to ground. t# NUP4304MR6 Configuration Options The nup4304Mr6 is able to protect up to four data lines lo 3 against transient overvoltage conditions by driving them to l'O 40. a fixed reference point for clamping purposes. The steering diodes will be forward biased whenever the voltage on the If additional protection of the supply rail is desired,an protected line exceeds the reference voltage(Vf or Vcc+Vf). external Tvs diode may be added across Vcc and ground The diodes will force the transient current to bypass the This will prevent overvoltage conditions on the supply rail ensitiye circuit protecting the supply and other circuits connected to it Data lines are connected at pins 1, 3, 4 and 6. The negative reference is connected at pin 5. This pin must be connected Option 3 directly to ground by using a ground plane to minimize the Protection of four data lines with bias and power supply PCBs ground inductance. It is very imporlant to reduce the isolation resistor PCB trace lengths as much as possible to minimize parasitic /O1 inductance /O2 Option 1 Protection of four data lines using vcc as reference l 10k /O1 /O2 3 HK /O3 10 4 The NUP4304MR6 can be isolated from the power supply by connecting a series resistor between pin 2 and Vcc. A /O3 10 kQ2 resistor is recommended for this application. This /O4 will maintain bias on the internal steering diodes, reducing their capacit For this configuration, connect pin 2 directly to the positive supply rail (vcc), the data lines are referenced to the ly voltage. Biasing of the steering diodes reduces their capacitance http://onsemi.co NUP4304MR6 Option 4 2 Protection of four data lines without biasing of the internal D3 5 steering lodes 6 1/0 2 D2 D4 D6 D8 NUP4304MR6 Equivalent Circuit / 3 1/0 4 In applications lacking a positive supply reference an external Tvs diode may be used as a reference. For these applications, the Tvs is connected between pin 2 and the ground plane. The steering diodes will conduct whenever the voltage on the protected line exceeds their forward voltage plus the working voltage of the TVs diode(vcvf Vrvs). In this case, the effective capacitance of the steering diodes will be higher than if a bias was applied http://onsemi.co NUP4304MR6 PACKAGE DIMENSIONS TSOP-6 CASE 318F-05 SSUE M NOTES 1. DIMENSIONING AND TOLERANCING PER ANS|Y145M,1982 2. CONTROLLING DIMENSION: INCH 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL HE E 4.318F-01,-02-030 BSOLETE.NEW STANDARD 318F-04 MILLIMETERS INCHES b DIM MIN NOM MAX MIN NOM MAX 0.90 11.100.0350c 0.043 0.U 0.06 C100.00110020.004 b025 03 C.50 00100.0150.020 0.18 004 0.010 D2903003.100.11401180122 060,A E1.3 501.700.05100590 095 0.40 C.60 0.00800160.024 2753c0009901080.118 A1 SOLDERING FOOTPRINTE 2.4 0.95 19 0.037 0.074 0.95 0.7 0.037 0028 0.039 SCALE 10: 1 For additional inf( on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D MicroIntegration is a trademark of Semiconductor Components Industries, LLC (SCILLC) ON Semiconductor and () arc registered trademarks of Semiconductor Components Industrics, LLC (SCILLC). SCILLC reserves the right to make changos without further notico Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. Al operating parameters, including "Typicals" must be validated for each customer applicatian by customer's technical experts. SCILLC does not convey any license under its patent ngts nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant in o the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLc oroduct could create a situation where personal injury or death may occur. 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