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NCP349-D Positive Overvoltage Protection Circuit-综合文档
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NCP349-D Positive Overvoltage Protection Circuit with Internal Low Ron NMOS FET
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© Semiconductor Components Industries, LLC, 2012
September, 2012 − Rev. 3
1 Publication Order Number:
NCP349/D
NCP349
Positive Overvoltage
Protection Controller with
Internal Low R
ON
NMOS FET
The NCP349 is able to disconnect the systems from its output pin
when wrong input operating conditions are detected. The system is
positive overvoltage protected up to +28 V.
This device uses an internal NMOS and therefore, no external
device is necessary, reducing the system cost and the PCB area of the
application board.
The NCP349 is able to instantaneously disconnect the output from
the input, due to integrated Low R
ON
Power NMOS (65 mW), if the
input voltage exceeds the overvoltage threshold (OVLO) or falls
below the undervoltage threshold (UVLO).
At powerup (EN pin = low level), the V
out
turns on t
on
time after
the V
in
exceeds the undervoltage threshold.
The NCP349 provides a negative going flag (FLAG) output, which
alerts the system that a fault has occurred.
In addition, the device has ESD−protected input (15 kV Air) when
bypassed with a 1.0 mF or larger capacitor.
Features
• Overvoltage Protection up to 28 V
• On−Chip Low R
DS(on)
NMOS Transistor: 65 mW
• Internal Charge Pump
• Overvoltage Lockout (OVLO)
• Undervoltage Lockout (UVLO)
• Soft−Start
• Alert FLAG Output
• Shutdown EN Input
• Compliance to IEC61000−4−2 (Level 4)
8.0 kV (Contact)
15 kV (Air)
• ESD Ratings: Machine Model = B
Human Body Model = 2
• DFN6 1.6x2 mm Package
• This is a Pb−Free Device
Applications
• Cell Phones
• Camera Phones
• Digital Still Cameras
• Personal Digital Applications
• MP3 Players
DFN6
MN SUFFIX
CASE 506BM
PIN CONNECTIONS
http://onsemi.com
MARKING DIAGRAM
XX = Specific Device Code
M = Date Code
G = Pb−Free Package
(Top View)
1
FLAG OUT
GND OUT
IN EN
Q
2
3
6
5
4
PAD1
IN
ORDERING INFORMATION
See detailed ordering, marking and shipping information in the
package dimensions section on page 11 of this data sheet.
1
6
XX MG
G
1
NCP349
http://onsemi.com
2
Figure 1. Typical Application Circuit
IN
7
OUT
5
GND
2
6
3
IN
1
OUT
4
NCP349
0
1 mF
10 k
Wall Adapter − AC/DC − USB
BATTERY
0
CC/CV
Charger or
System
V
Bat
ENABLE/
Microprocessor
EN
FLAG
mP
Figure 2. Functional Block Diagram
INPUT
OUTPUT
UVLO
OVLO
Gate
Driver
FLAG
EN
EN Block
V
REF
Charge
Pump
Control
Logic and
Timer
GND
7
1
6
2
3
5
4
NCP349
http://onsemi.com
3
PIN FUNCTION DESCRIPTION
Pin No. Symbol Function Description
1, 7 IN INPUT Input Voltage Pins. These pins are connected to the Wall Adapoter (AC−DC, Vbus ..). A 1 mF low
ESR ceramic capacitor, or larger, must be connected between these pins and GND, as close as
possible to the DUT. The two IN pins must be connected together to power supply. (See PCB
recommendation for the pin7).
2 GND POWER Ground
3 FLAG OUTPUT Fault Indication Pin. This pin allows an external system to detect a fault on the IN pins. The FLAG pin
goes low when input voltage exceeds OVLO threshold or drops below UVLO threshold. Since the
FLAG pin is open drain functionality, an external pull−up resistor to V
CC
must be added. (Minimum
10 kW).
4, 5 OUT OUTPUT Output Voltage Pins. These pins follow IN pins when “no fault” is detected. The two OUT pins must
be hardwired together.
6 EN INPUT Enable Pin. The device enters in shutdown mode when this pin is tied to a high level. In this case the
output is disconnected from the input. To allow normal functionality, the EN pin shall be connected to
GND to a pull down or to a I/O pin. This pin does not have an impact on the fault detection.
MAXIMUM RATINGS
Rating Symbol Value Unit
Minimum Voltage (IN to GND) Vmin
in
−0.3 V
Minimum Voltage (All others to GND) Vmin −0.3 V
Maximum Voltage (IN to GND) Vmax
in
30 V
Maximum Voltage (All others to GND) Vmax 7.0 V
Maximum Current (UVLO<V
IN
<OVLO) Imax 2.0 A
Maximum Peak Current (t ≤ 1 ms, T
A
= 85°C) Imax
peak
4.0 A
Thermal Resistance, Junction−to−Air (Note 1) R
q
JA
180 °C/W
Operating Ambient Temperature Range T
A
−40 to +85 °C
Storage Temperature Range T
stg
−65 to +150 °C
Junction Operating Temperature T
J
150 °C
ESD Withstand Voltage (IEC 61000−4−2) (input only) when bypassed with 1.0 mF capacitor
Human Body Model (HBM), Model = 2 (Note 2)
Machine Model (MM) Model = B (Note 3)
Vesd 15 Air, 8.0 Contact
2000
200
kV
V
V
Moisture Sensitivity MSL Level 1 −
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The R
q
JA
is highly dependent on the PCB heat sink area (connected to pin 7).
2. Human Body Model, 100 pF discharged through a 1.5 kW resistor following specification JESD22/A114.
3. Machine Model, 200 pF discharged through all pins following specification JESD22/A115.
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