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July, 2020 − Rev. 2

1 Publication Order Number:

NCP1362/D

Primary Side PWM

Controller for Low Power

Offline SMPS

NCP1362

The NCP1362 offers a new solution targeting output power levels

from a few watts up to 50 W in a universal−mains flyback application.

Thanks to a Novel Method this new controller saves the secondary

feedback circuitry for Constant Voltage and Constant Current

regulation, achieving excellent line and load regulation without

traditional opto coupler and TL431 voltage reference.

The NCP1362 operates in valley lockout quasi−resonant peak

current mode control mode at high load to provide high efficiency.

When the power on the secondary side starts to diminish, the

controller automatically adjusts the duty−cycle then at lower load the

controller enters in pulse frequency modulation at fixed peak current

with a valley switching detection. This technique allows keeping the

output regulation with tiny dummy load. Valley lockout at the first 4

valleys prevent valley jumping operation and then a valley switching

at lower load provides high efficiency.

Features

• Constant Voltage Primary−Side Regulation < ±5%

• Constant Current Primary−Side Regulation < ±5%

• LFF and BO Feature on a Dedicated Pin:

♦ BO Detection

♦ LFF for CC Regulation Improvement

• Quasi−Resonant with Valley Switching Operation

• Optimized Light Load Efficiency and Stand−by Performance

• Maximum Frequency Clamp (No Clamp, 80, 110 and 140 kHz)

• Cycle by Cycle Peak Current Limit

• Output Voltage Under Voltage and Over Voltage Protection

(UVP or OVP)

• Secondary Diode or Winding Short−Circuit Protection

• Wide Operation V

Range (up to 28 V)

• Low Start−up Current

• CS & V

/ZCD Pin Short and Open Protection

• Internal Temperature Shutdown

• Internal and Fixed Frequency Jittering for Better EMI Signature

• Dual Frozen Peak Current to Both Optimize Light Load Efficiency

(10% Load) and Stand−by Performance (No−load)

• Fault Input for Severe Fault Conditions, NTC Compatible for OTP

• These are Pb−Free Devices

Applications

• Low Power ac−dc Adapters for Routers and Set−Top Box

• Low Power ac−dc Adapters for Chargers

www.onsemi.com

See detailed ordering and shipping information on page 28 of

this data sheet.

ORDERING INFORMATION

MARKING DIAGRAM

SOIC−8

CASE 751AZ

IC (Pb−Free)

P1362yy

ALYW

P1362yy = Specific Device Code

(See page 28)

A = Assembly Location

L = Wafer Lot

Y = Year

W = Work Week

G = Pb−Free Package

PINOUT DIAGRAM

(Top View)

DRV

GND

VCC

BO/LFF

Fault

COMP

Vs/ZCD

NCP1362

www.onsemi.com

Table 1. PIN FUNCTION DESCRIPTION

Pin Name Function

1 V

/ZCD Connected to the auxiliary winding; this pin senses the voltage output for the primary regula-

tion and detects the core reset event for the Quasi−Resonant mode of operation.

2 Comp This is the error amplifier output. The network connected between this pin and the ground

adjusts the regulation loop bandwidth.

3 Fault The controller enters in fault mode if the voltage of this pin is pulled above or below the fault

thresholds. A precise pullup current allows direct interface with an NTC thermistor. Fault de-

tection triggers a latch.

4 CS This pin monitors the primary peak current.

5 DRV The driver’s output to an external MOSFET gate.

6 GND Ground reference.

7 V

This pin is connected to an external auxiliary voltage and supplies the controller.

8 BO/LFF Detects too low input voltage conditions (Brown−Out). Also voltage pin level is used for build-

ing Line FeedForward compensation for improving Constant Current regulation tolerance.

Table 2. MAXIMUM RATINGS (Note 1)

Symbol

Rating Value Unit

CC(MAX)

Maximum Power Supply voltage, V

pin, continuous voltage

Maximum current for V

−0.3 to 28

Internally limited

/Dt

Maximum slew rate on V

pin during start−up phase +0.4

V/ms

Single Pulse Avalanche Rating 120 mJ

MAX

Maximum voltage on low power pins (except pins DRV and VCC)

Current range for low power pins (except pins DRV and VCC)

−0.3, 5.5

−2, +5

DRV(MAX)

Maximum driver pin voltage, DRV pin, continuous voltage

Maximum current for DRV pin

−0.3, V

DRV

(Note 2)

−300, +500

J−A

Thermal Resistance Junction−to−Air, 2.0 oz Printed Circuit Copper Clad 190 °C/W

J(MAX)

Maximum Junction Temperature 150 °C

Operating Temperature Range −40 to +125 °C

Storage Temperature Range −60 to +150 °C

Human Body Model ESD Capability per JEDEC JESD22−A114F 2 kV

Machine Model ESD Capability (All pins except DRV) per JEDEC JESD22−A115C 200 V

Charged−Device Model ESD Capability per JEDEC JESD22−C101E 500 V

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality

should not be assumed, damage may occur and reliability may be affected.

1. This device contains latch−up protection and exceeds 100 mA per JEDEC Standard JESD78.

2. V

DRV

is the DRV clamp voltage V

DRV(high)

when V

is higher than V

DRV(high)

. V

DRV

is V

otherwise.

NCP1362

www.onsemi.com

Table 3. ELECTRICAL CHARACTERISTICS

= 12 V, For typical values T

= 25°C, for min/max values T

= −40°C to +125°C, Max T

= 150°C, unless otherwise noted)

Characteristics

Condition Symbol Min Typ Max Unit

SUPPLY SECTION AND V

MANAGEMENT

Level at which Driving Pulses

are Authorized

increasing V

CC(on)

16 18 20 V

Level at which Driving Pulses

are Stopped

decreasing V

CC(off)

6.0 6.5 7.0 V

Internal Latch/Logic Reset

Level

CC(reset)

− 6.25 − V

Internal Autorecovery Reset Level (Note 4) V

CC(reset_auto)

0.6 − − V

Hysteresis above V

CC(off)

for Fast

Hiccup in Latch Mode

CC(latch_hyst)

− 0.2 − V

Hysteresis below V

CC(off)

before Latch Reset

CC(reset_hyst)

0.15 0.30 0.50 V

Over Voltage Protection Over Voltage threshold V

CC(OVP)

24 26 28 V

Start−up Supply Current,

Controller Disabled or Latched

< V

CC(on)

& V

increasing from 0 V

CC(start)

– 3.6 5.5

Internal IC Consumption, Steady

State

= 65 kHz

= 1 nF

CC(steady)

– 1.6 2.3 mA

Internal IC Consumption in

Minimum Frequency Clamp

VCO mode, F

= f

VCO(min)

Comp

= GND

VCO(min)

= 1 kHz

VCO(min)

= 200 Hz

= 1 nF

CC(VCO)

–

325

210

430

370

Internal IC Consumption in Fault

Mode (after a fault when V

decreasing to V

CC(off)

)

Autorecovery mode I

CC(auto)

– 2.0 2.2 mA

Internal IC Consumption in Fault

Mode (after a fault when V

decreasing to V

CC(off)

)

Latch mode I

CC(latch)

– 1.0 1.2 mA

CURRENT COMPARATOR

Current Sense Voltage

Threshold

Comp

= V

Comp(max)

increasing

ILIM

0.76 0.8 0.84 V

Cycle by Cycle Leading Edge

Blanking Duration

LEB1

250 320 380 ns

Cycle by Cycle Current Sense

Propagation Delay

> (V

ILIM

+ 100 mV) to

DRV turn−off

ILIM

– 50 110 ns

Timer Delay before Detecting an

Overload Condition

When CS pin w V

ILIM

(Note 3)

OCP

50 70 90 ms

Threshold for Immediate Fault

Protection Activation

CS(stop)

1.08 1.2 1.32 V

Leading Edge Blanking

Duration for V

CS(stop)

LEB2

− 120 − ns

Maximum Peak Current Level at

which VCO Takes Over or Frozen

Peak Current

increasing

0.6 V < V

Comp

< 1.9 V

(other possible options on

demand)

CS(VCO)

− 250 − mV

Minimum Peak Current Level V

increasing

Comp

< 0.2 V

(other possible options on

demand)

CS(STB)

− 65 − mV

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product

performance may not be indicated by the Electrical Characteristics if operated under different conditions.

3. The timer can be reset if there are 4 DRV cycles without overload or short circuit conditions.

4. Guaranteed by Design.

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