Chin. Phys. B Vol. 21, No. 6 (2012) 068501
A low on-resistance triple RESURF SOI LDMOS with
planar and trench gate integration
∗
Luo Xiao-Rong(罗小蓉)
a)b)†
, Yao Guo-Liang(姚国亮)
a)
, Zhang Zheng-Yuan(张正元)
b)
,
Jiang Yong-Heng(蒋永恒)
a)
, Zhou Kun(周 坤)
a)
, Wang Pei(王 沛)
a)
, Wang Yuan-Gang(王元刚)
a)
,
Lei Tian-Fei(雷天飞)
a)
, Zhang Yun-Xuan(张云轩)
a)
, and Wei Jie(魏 杰)
a)
a)
State Key Laboratory of Electronic Thin Films and Integrated Devices. University of Electronic Science
and Technology of China, Chengdu 610054, China
b)
No. 24 Research Institute of China Electronics Technology Group Corporation, Chongqing 400060, China
(Received 23 September 2011; revised manuscript received 17 November 2011)
A low on-resistance (R
on,sp
) integrable silicon-on-insulator (SOI) n-channel lateral double-diffused metal–oxide–
semiconductor (LDMOS) is proposed and its mechanism is investigated by simulation. The LDMOS has two features:
the integration of a planar gate and an extended trench gate (double gates (DGs)); and a buried P-layer in the N-drift
region, which forms a triple reduced surface field (RESURF) (TR) structure. The triple RESURF not only modulates
the electric field distribution, but also increases N-drift doping, resulting in a reduced specific on-resistance (R
on,sp
)
and an improved breakdown voltage (BV) in the off-state. The DGs form dual conduction channels and, moreover, the
extended trench gate widens the vertical conduction area, both of which further reduce the R
on,sp
. The BV and R
on,sp
are 328 V and 8.8 mΩ · cm
2
, respectively, for a DG TR metal–oxide–semiconductor field-effect transistor (MOSFET)
by simulation. Compared with a conventional SOI LDMOS, a DG TR MOSFET with the same dimensional device
parameters as those of the DG TR MOSFET reduces R
on,sp
by 59% and increases BV by 6%. The extended trench gate
synchronously acts as an isolation trench between the high-voltage device and low-voltage circuitry in a high-voltage
integrated circuit, thereby saving the chip area and simplifying the fabrication processes.
Keywords: SOI, electric field, breakdown voltage, trench gate, specific on-resistance
PACS: 85.30.De, 85.30.Tv, 84.70.p DOI: 10.1088/1674-1056/21/6/068501
1. Introduction
Lateral double-diffused metal–oxide–semicondu-
ctor (LDMOS) field effect transistors are widely used
in smart p ower integrated circuits (ICs) due to their
ease of integration and drive. The on-resistance (R
on
)
increases with breakdown voltage (BV) as R
on
∝
BV
2.5
in a conventional power LDMOS,
[1]
result-
ing in an increase in power loss. The reduced sur-
face field (RESURF) technique is always employed to
achieve the trade-off between R
on
and BV.
[2−6]
Trench
gate metal–oxide–semiconductor field-effect transis-
tors (MOSFETs) further reduce the value of R
on
because of the high channel density and the elimi-
nation of the junction field effect transistor (JFET)
effect.
[7−14]
Two structures, in which the gate and
the source or the gate and the drain were placed in
one trench, were used to reduce the cell pitch and
R
on,sp
.
[10,11]
Unfortunately, these are good options
only for MOSFETs with BV < 100 V, owing to the
complex fabrication process and weakened effect for
devices with a higher BV. The purpose of this paper
is (i) to realize a high BV, (ii) to minimize the on-state
loss, and (iii) to isolate the low-voltage circuitry from
high-voltage devices in power ICs.
Combining the RESURF technique with the mer-
its of trench gate MOSFETs and LDMOSFETs as
mentioned above, we propose a double gate (DG)
triple RESURF (TR) SOI LDMOS, which integrates
a trench gate and a planar gate. The DGs form dual
conduction channels, thereby reducing the value of
R
on,sp
. Furthermore, the buried p-layer (BP) and the
N-drift region form a triple RESURF, thereby increas-
ing the N-drift doping and reshaping the electric field
distribution. A reduced R
on
and an improved BV are
therefore obtained. The extended trench gate realizes
the isolation in a high-voltage IC, with the DG TR
MOSFET serving as its power device.
∗
Project supported by the National Natural Science Foundation of China (Grant Nos. 61176069 and 609 76060) and the National
Key Laboratory of Analogue Integrated Circuit (Grant No. 9140C090304110C0905).
†
Corresponding author. E-mail: xrluo@uestc.edu.cn
c
2012 Chinese Physical Society and IOP Publishing Ltd
http://iopscience.iop.org/cpb
http://cpb.iphy.ac.cn
068501-1
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