A 600V-class Partial SOI LDMOS with Step-doped Drift Region
Yue Hu
1,2,a
, Hao Wang
1,b
, Dewen Wang
3,c
, Caixia Du
1,d
, Miaomiao Ma
1,e
,
Jin Yang
1,f
, and Jin He
1,2,g
1
Peking University Shenzhen SOC Key Laboratory, Shenzhen 518055, P. R. China
2
School of Electronics Engineering and Computer Science, P. R. China
3
SHENZHEN SI Semiconductors CO., Ltd, Longgang, Shenzhen 518057, P. R. China
a
mocoshu@qq.com,
b
wanghaosoc1@126.com,
c
wangdw@sisemi.com.cn,
d
ducaixia@ime.pku.edu.cn,
e
mamiaomiaosoc@126.com ,
f
szlab.jin@gmail.com,
g
frankhe@pku.edu.cn
Keywords: Breakdown voltage (BV), on-resistance (Ron), partial silicon-on-insulator (PSOI), lateral
double-diffused Metal-oxide-semiconductor (LDMOS).
Abstract: A 600V-class lateral double-diffused metal-oxide-semiconductor (LDMOS) field-effect
transistor with step-doped drift region (SDD) in partial silicon-on-insulator (PSOI) is introduced to
improve breakdown voltage (BV) and reduce on-resistance (Ron). The step-doped method induces an
electric field peak in the surface of the device, which can reduce the surface field in the device and
adjust the doping accommodation in the drift region. The adjusted drift region can allow higher
doping concentration under the drain end which results in higher breakdown voltage, and
accommodate more impurity atoms as a whole which provides more electrons to support higher
current and thus reduce on-resistance.
Introduction
Lateral double-diffused metal-oxide-semiconductor field-effect transistors (LDMOSFETs) have
been attracting a great deal of attention in smart power integrated circuit applications [1-4]. Due to
advantages such as low leakage current, ideal isolation between devices and higher switching speed
[5], silicon-on-insulator (SOI) technology is introduced into lateral double- diffused
metal-oxide-semiconductors (LDMOSs). In recent years, high-voltage LDMOSFETs have been
explored in partial silicon-on-insulator (PSOI) technology [6-8], because of its higher breakdown
voltage and better thermal effect in comparison with SOI technology [9-10]. However, due to the
limitation of the silicon material and thickness of the buried-oxide layer (BOX) [11], it is found that
breakdown voltage (BV) is very difficult to achieve exceeding 600V for both SOI and PSOI structures.
In order to improve the BV of SOI and PSOI LDMOSs, some efforts have been put into altering the
shape or the material of BOX layer [12-14]
In this work, a novel 600V-class PSOI LDMOSFET is introduced. This new PSOI LDMOSFET is
designed by using step-doped drift (SDD) region instead of uniform doping drift region in the
LDMOS structure. The key performance of the proposed device structure can result in obvious
improvements by comparison with those of conventional SOI (CSOI) and PSOI (CPSOI). All
simulation results are analyzed through 2-D simulations by using Sentaurus TCAD.
Device design
A cross-sectional schematic of the proposed SDD-PSOI is shown in Fig. 1 (a), in which the drift
region is divided into two parts with different doping concentrations. The lateral location x
P
of the
interface between the drift1 and drift2 region, the coordinate axes and the origin point O are illustrated
in Fig. 1 (a).
Generally, the doping concentration of the drift2 is larger than that of the drift1 in the device
design, which is shown in Fig.1 (b). The reason is that the higher doping concentration can induce
Advanced Materials Research Vol. 1096 (2015) pp 514-519 Submitted: 03.09.2014
© (2015) Trans Tech Publications, Switzerland Accepted: 07.11.2014
doi:10.4028/www.scientific.net/AMR.1096.514