Verilog HDL主从触发器举例

主从D触发器的门级描述如下：module MSDFF (D,C,Q,Qbar);input D,C;output Q,Qbar;not NT1 (NotD,D),NT2 (NotC,C),NT3 (NotY,Y);nandND1 (D1,D,C),ND2 (D2,C,NotD),ND3 (Y,D1,Ybar),ND4 (Ybar,Y,D2),ND5 (Y1,Y,NotC),ND6 (Y2,NotY,NotC),ND7 (Q,Qbar,Y1),ND8 (Qbar,Y2,Q);endmodule