没有合适的资源?快使用搜索试试~ 我知道了~
AM29LV256M.pdf
需积分: 34 27 下载量 55 浏览量
2009-03-31
04:28:36
上传
评论 1
收藏 1.52MB PDF 举报
温馨提示
试读
70页
AM29LV256M.pdfAM29LV256M.pdfAM29LV256M.pdf
资源推荐
资源详情
资源评论
September 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Am29LV256M
Data Sheet
Publication Number 25263 Revision C Amendment +3 Issue Date September 15, 2003
THIS PAGE LEFT INTENTIONALLY BLANK.
DATASHEET
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 25263 Rev: C Amendment/+3
Issue Date: September 15, 2003
Refe
r t
o
AMD’
s
Webs
it
e
(www.a
m
d.co
m
)
fo
r th
e
l
a
t
es
t in
fo
rm
a
ti
o
n
.
Am29LV256M
256 Megabit (16 M x 16-Bit/32 M x 8-Bit) MirrorBit
TM
3.0 Volt-only
Uniform Sector Flash Memory with VersatileI/O
TM
Control
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
Single power supply operation
— 3 volt read, erase, and program operations
VersatileI/O
TM
control
— Device generates data output voltages and tolerates
data input voltages on the CE# and DQ inputs/outputs
as determined by the voltage on the V
IO
pin; operates
from 1.65 to 3.6 V
Manufactured on 0.23 µm MirrorBit process
technology
SecSi
TM
(Secured Silicon) Sector region
— 128-word/256-byte sector for permanent, secure
identification through an 8-word/16-byte random
Electronic Serial Number, accessible through a
command sequence
— May be programmed and locked at the factory or by
the customer
Flexible sector architecture
— Five hundred twelve 32 Kword (64 Kbyte) sectors
Compatibility with JEDEC standards
— Provides pinout and software compatibility for
single-power supply flash, and superior inadvertent
write protection
Minimum 100,000 erase cycle guarantee per sector
20-year data retention at 125°C
PERFORMANCE CHARACTERISTICS
High performance
— 100 ns access time
— 30 ns page read times
— 0.5 s typical sector erase time
— 15 µs typical effective write buffer word programming
time: 16-word/32-byte write buffer reduces overall
programming time for multiple-word updates
— 4-word/8-byte page read buffer
— 16-word/32-byte write buffer
Low power consumption (typical values at 3.0 V, 5
MHz)
— 13 mA typical active read current
— 50 mA typical erase/program current
— 1 µA typical standby mode current
Package options
— 56-pin TSOP
— 64-ball Fortified BGA
SOFTWARE & HARDWARE FEATURES
Software features
— Program Suspend & Resume: read other sectors
before programming operation is completed
— Erase Suspend & Resume: read/program other
sectors before an erase operation is completed
— Data# polling & toggle bits provide status
— Unlock Bypass Program command reduces overall
multiple-word or byte programming time
— CFI (Common Flash Interface) compliant: allows host
system to identify and accommodate multiple flash
devices
Hardware features
— Sector Group Protection: hardware-level method of
preventing write operations within a sector group
— Temporary Sector Group Unprotect: V
ID
-level method
of changing code in locked sector groups
— WP#/ACC input accelerates programming time
(when high voltage is applied) for greater throughput
during system production. Protects first or last sector
regardless of sector protection settings
— Hardware reset input (RESET#) resets device
— Ready/Busy# output (RY/BY#) detects program or
erase cycle completion
2 Am29LV256M September 15, 2003
DATASHEET
GENERAL DESCRIPTION
The Am29LV256M is a 256 Mbit, 3.0 volt single power
supply flash memory devices organized as 16,777,216
words or 33,554,432 bytes. The device has a 16-bit
wide data bus that can also function as an 8-bit wide
data bus by using the BYTE# input. The device can be
programmed either in the host system or in standard
EPROM programmers.
An access time of 100, 110, or 120 ns is available.
Note that each access time has a specific operating
voltage range (V
CC
) and an I/O voltage range (V
IO
), as
specified in the Product Selector Guide and the Order-
ing Information sections. The device is offered in a
56-pin TSOP or Fortified BGA package. Each device
has separate chip enable (CE#), write enable (WE#)
and output enable (OE#) controls.
Each device requires only a single 3.0 volt power
supply for both read and write functions. In addition to
a V
CC
input, a high-voltage accelerated program
(WP#/ACC) input provides shorter programming times
through increased current. This feature is intended to
facilitate factory throughput during system production,
but may also be used in the field if desired.
The device is entirely command set compatible with
the JEDEC single-power-supply Flash standard.
Commands are written to the device using standard
microprocessor write timing. Write cycles also inter-
nally latch addresses and data needed for the pro-
gramming and erase operations.
The sector erase architecture allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Device programming and erasure are initiated through
command sequences. Once a program or erase oper-
ation has begun, the host system need only poll the
DQ7 (Data# Polling) or DQ6 (toggle) status bits or
monitor the Ready/Busy# (RY/BY#) output to deter-
mine whether the operation is complete. To facilitate
programming, an Unlock Bypass mode reduces com-
mand sequence overhead by requiring only two write
cycles to program data instead of four.
The VersatileI/O™ (V
IO
) control allows the host sys-
tem to set the voltage levels that the device generates
and tolerates on the CE# control input and DQ I/Os to
the same voltage level that is asserted on the V
IO
pin.
Refer to the Ordering Information section for valid V
IO
options.
Hardware data protection measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
group protection feature disables both program and
erase operations in any combination of sector groups
of memory. This can be achieved in-system or via pro-
gramming equipment.
The Erase Suspend/Erase Resume feature allows
the host system to pause an erase operation in a
given sector to read or program any other sector and
then complete the erase operation. The Program
Suspend/Program Resume feature enables the host
system to pause a program operation in a given sector
to read any other sector and then complete the pro-
gram operation.
The hardware RESET# pin terminates any operation
in progress and resets the device, after which it is then
ready for a new operation. The RESET# pin may be
tied to the system reset circuitry. A system reset would
thus also reset the device, enabling the host system to
read boot-up firmware from the Flash memory device.
The device reduces power consumption in the
standby mode when it detects specific voltage levels
on CE# and RESET#, or when addresses have been
stable for a specified period of time.
The SecSi
TM
(Secured Silicon) Sector provides a
128-word/256-byte area for code or data that can be
permanently protected. Once this sector is protected,
no further changes within the sector can occur.
The Write Protect (WP#/ACC) feature protects the
first or last sector by asserting a logic low on the WP#
pin.
AMD MirrorBit flash technology combines years of
Flash memory manufacturing experience to produce
the highest levels of quality, reliability and cost effec-
tiveness. The device electrically erases all bits within a
sector simultaneously via hot-hole assisted erase. The
data is programmed using hot electron injection.
RELATED DOCUMENTS
For a comprehensive information on MirrorBit prod-
ucts, including migration information, data sheets, ap-
plication notes, and software drivers, please see
www.amd.com
→Flash Memory→Product Informa-
tion
→MirrorBit→Flash Information→Technical Docu-
mentation. The following is a partial list of documents
closely related to this product:
MirrorBit™ Flash Memory Write Buffer Programming
and Page Buffer Read
Implementing a Common Layout for AMD MirrorBit
and Intel StrataFlash Memory Devices
Migrating from Single-byte to Three-byte Device IDs
September 15, 2003 Am29LV256M 3
DATASHEET
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . 5
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 9
Table 1. Device Bus Operations ....................................................... 9
Word/Byte Configuration .......................................................... 9
VersatileIO
TM
(V
IO
) Control ........................................................ 9
Requirements for Reading Array Data ................................... 10
Page Mode Read ............................................................................10
Writing Commands/Command Sequences ............................ 10
Write Buffer .....................................................................................10
Accelerated Program Operation ......................................................10
Autoselect Functions .......................................................................10
Standby Mode ........................................................................ 10
Automatic Sleep Mode ........................................................... 11
RESET#: Hardware Reset Pin ............................................... 11
Output Disable Mode .............................................................. 11
Table 2. Sector Address Table........................................................ 12
Autoselect Mode ..................................................................... 23
Table 3. Autoselect Codes, (High Voltage Method) ....................... 23
Sector Group Protection and Unprotection ............................. 24
Table 4. Sector Group Protection/Unprotection Address Table ..... 24
Write Protect (WP#) ................................................................ 26
Temporary Sector Group Unprotect ....................................... 26
Figure 1. Temporary Sector Group Unprotect Operation ................26
Figure 2. In-System Sector Group Protect/Unprotect Algorithms ...27
SecSi (Secured Silicon) Sector Flash Memory Region .......... 28
Table 5. SecSi Sector Contents ...................................................... 28
................................................................................................ 29
Figure 3. SecSi Sector Protect Verify ..............................................29
Hardware Data Protection ...................................................... 29
Low VCC Write Inhibit .....................................................................29
Write Pulse “Glitch” Protection ........................................................29
Logical Inhibit ..................................................................................29
Power-Up Write Inhibit ....................................................................29
Common Flash Memory Interface (CFI) . . . . . . . 29
Table 6. CFI Query Identification String ..........................................30
Table 7. System Interface String..................................................... 30
Table 8. Device Geometry Definition ..............................................31
Table 9. Primary Vendor-Specific Extended Query ........................32
Command Definitions . . . . . . . . . . . . . . . . . . . . . 32
Reading Array Data ................................................................ 32
Reset Command ..................................................................... 33
Autoselect Command Sequence ............................................ 33
Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 33
Word/Byte Program Command Sequence ............................. 33
Unlock Bypass Command Sequence ..............................................34
Write Buffer Programming ...............................................................34
Accelerated Program ......................................................................35
Figure 4. Write Buffer Programming Operation ...............................36
Figure 5. Program Operation ..........................................................37
Program Suspend/Program Resume Command Sequence ... 37
Figure 6. Program Suspend/Program Resume ...............................38
Chip Erase Command Sequence ........................................... 38
Sector Erase Command Sequence ........................................ 38
Table 10. Erase Operation ............................................................. 39
Erase Suspend/Erase Resume Commands ........................... 39
Command Definitions ............................................................. 40
Table 11. Command Definitions (x16 Mode, BYTE# = V
IH
) ........... 40
Table 12. Command Definitions (x8 Mode, BYTE# = V
IL
).............. 41
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 42
DQ7: Data# Polling ................................................................. 42
Figure 7. Data# Polling Algorithm .................................................. 42
RY/BY#: Ready/Busy# ............................................................ 43
DQ6: Toggle Bit I .................................................................... 43
Figure 8. Toggle Bit Algorithm ........................................................ 44
DQ2: Toggle Bit II ................................................................... 44
Reading Toggle Bits DQ6/DQ2 ............................................... 44
DQ5: Exceeded Timing Limits ................................................ 45
DQ3: Sector Erase Timer ....................................................... 45
DQ1: Write-to-Buffer Abort ..................................................... 45
Table 13. Write Operation Status................................................... 45
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 46
Figure 9. Maximum Negative Overshoot Waveform ..................... 46
Figure 10. Maximum Positive Overshoot Waveform ..................... 46
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 46
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 47
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 11. Test Setup ..................................................................... 48
Table 14. Test Specifications ......................................................... 48
Key to Switching Waveforms. . . . . . . . . . . . . . . . 48
Figure 12. Input Waveforms and
Measurement Levels ...................................................................... 48
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 49
Read-Only Operations ............................................................ 49
Figure 13. Read Operation Timings ............................................... 49
Figure 14. Page Read Timings ...................................................... 50
Hardware Reset (RESET#) .................................................... 51
Figure 15. Reset Timings ............................................................... 51
Erase and Program Operations .............................................. 52
Figure 16. Program Operation Timings .......................................... 53
Figure 17. Accelerated Program Timing Diagram .......................... 53
Figure 18. Chip/Sector Erase Operation Timings .......................... 54
Figure 19. Data# Polling Timings (During Embedded Algorithms) . 55
Figure 20. Toggle Bit Timings (During Embedded Algorithms) ...... 56
Figure 21. DQ2 vs. DQ6 ................................................................. 56
Temporary Sector Unprotect .................................................. 57
Figure 22. Temporary Sector Group Unprotect Timing Diagram ... 57
Figure 23. Sector Group Protect and Unprotect Timing Diagram .. 58
Alternate CE# Controlled Erase and Program Operations ..... 59
Figure 24. Alternate CE# Controlled Write (Erase/Program)
Operation Timings .......................................................................... 60
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 60
Erase And Programming Performance. . . . . . . . 61
TSOP Pin and BGA Package Capacitance . . . . . 61
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 63
TS056/TSR056—56-Pin Standard/Reverse Thin Small Outline
Package (TSOP) ..................................................................... 63
LAC064—64-Ball Fortified Ball Grid Array
18 x 12 mm Package .............................................................. 64
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 65
剩余69页未读,继续阅读
资源评论
wangdayuno1
- 粉丝: 0
- 资源: 22
上传资源 快速赚钱
- 我的内容管理 展开
- 我的资源 快来上传第一个资源
- 我的收益 登录查看自己的收益
- 我的积分 登录查看自己的积分
- 我的C币 登录后查看C币余额
- 我的收藏
- 我的下载
- 下载帮助
安全验证
文档复制为VIP权益,开通VIP直接复制
信息提交成功