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Contents
1. Embedded Peripherals IP User Guide Introduction....................................................... 19
1.1. Tool Support....................................................................................................... 19
1.2. Device Support....................................................................................................20
1.3. Embedded Peripheral IP User Guide Introduction Revision History...............................20
2. Avalon-ST Multi-Channel Shared Memory FIFO Core..................................................... 22
2.1. Core Overview.....................................................................................................22
2.2. Performance and Resource Utilization..................................................................... 22
2.3. Functional Description.......................................................................................... 23
2.3.1. Interfaces............................................................................................... 24
2.3.2. Operation............................................................................................... 24
2.4. Parameters......................................................................................................... 25
2.5. Software Programming Model................................................................................ 26
2.5.1. HAL System Library Support......................................................................26
2.5.2. Register Map........................................................................................... 26
2.6. Avalon-ST Multi-Channel Shared Memory FIFO Core Revision History.......................... 27
3. Avalon-ST Single-Clock and Dual-Clock FIFO Cores.......................................................28
3.1. Core Overview.....................................................................................................28
3.2. Functional Description.......................................................................................... 28
3.2.1. Interfaces............................................................................................... 29
3.2.2. Operating Modes......................................................................................29
3.2.3. Fill Level................................................................................................. 30
3.2.4. Thresholds.............................................................................................. 30
3.3. Parameters......................................................................................................... 31
3.4. Register Description............................................................................................. 31
3.5. Avalon-ST Single-Clock and Dual-Clock FIFO Core Revision History............................ 32
4. Avalon-ST Serial Peripheral Interface Core................................................................... 34
4.1. Core Overview.....................................................................................................34
4.2. Functional Description.......................................................................................... 34
4.2.1. Interfaces............................................................................................... 34
4.2.2. Operation............................................................................................... 35
4.2.3. Timing....................................................................................................36
4.2.4. Limitations..............................................................................................36
4.3. Configuration...................................................................................................... 36
4.4. Avalon-ST Serial Peripheral Interface Core Revision History....................................... 36
5. SPI Core........................................................................................................................37
5.1. Core Overview.....................................................................................................37
5.2. Functional Description.......................................................................................... 37
5.2.1. Example Configurations............................................................................ 38
5.2.2. Transmitter Logic..................................................................................... 39
5.2.3. Receiver Logic......................................................................................... 39
5.2.4. Master and Slave Modes........................................................................... 39
5.3. Configuration...................................................................................................... 41
5.3.1. Master/Slave Settings...............................................................................41
5.3.2. Data Register Settings.............................................................................. 42
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5.3.3. Timing Settings....................................................................................... 42
5.4. Software Programming Model................................................................................ 43
5.4.1. Hardware Access Routines.........................................................................43
5.4.2. Software Files..........................................................................................44
5.4.3. Register Map........................................................................................... 45
5.5. SPI Core Revision History......................................................................................48
6. SPI Slave/JTAG to Avalon Master Bridge Cores.............................................................49
6.1. Core Overview.....................................................................................................49
6.2. Functional Description.......................................................................................... 49
6.3. Parameters......................................................................................................... 52
6.4. SPI Slave/JTAG to Avalon Master Bridge Cores Revision History..................................52
7. Intel eSPI Slave Core.................................................................................................... 53
7.1. Functional Description.......................................................................................... 54
7.1.1. Link Layer...............................................................................................54
7.1.2. Transaction Layer.....................................................................................56
7.1.3. Channel Specific Layer..............................................................................56
7.1.4. Port80 Implementation............................................................................. 59
7.1.5. VW message to Physical Port Implementation.............................................. 59
7.1.6. Avalon-MM Interface Settings.................................................................... 60
7.2. Resource Utilization..............................................................................................61
7.3. IP Parameters..................................................................................................... 61
7.4. Interface Signals..................................................................................................62
7.5. Registers............................................................................................................ 64
7.5.1. Avalon-MM Interface Accessible Registers....................................................64
7.5.2. eSPI Interface Accessible Registers............................................................ 66
7.6. Peripheral Channel Avalon Interface Use Model........................................................ 69
7.7. Intel eSPI Slave Core Revision History.................................................................... 70
8. eSPI to LPC Bridge Core................................................................................................ 71
8.1. Unsupported LPC Features.................................................................................... 71
8.2. IP Parameters..................................................................................................... 71
8.3. Supported IP Clock Frequency............................................................................... 72
8.4. Functional Description.......................................................................................... 73
8.4.1. FIFO Implementation................................................................................73
8.4.2. Transaction Ordering Rule......................................................................... 74
8.4.3. eSPI Command to LPC Cycle Type Conversion..............................................75
8.4.4. SERIRQ Interrupt Event............................................................................ 75
8.5. Interface Signals..................................................................................................77
8.6. Registers............................................................................................................ 79
8.6.1. Status Register........................................................................................ 79
8.6.2. Error Register..........................................................................................80
8.7. eSPI to LPC Bridge Core Revision History................................................................ 80
9. Ethernet MDIO Core...................................................................................................... 81
9.1. Core Overview.....................................................................................................81
9.2. Functional Description.......................................................................................... 81
9.2.1. MDIO Frame Format (Clause 45)................................................................82
9.2.2. MDIO Clock Generation.............................................................................83
9.2.3. Interfaces............................................................................................... 83
9.2.4. Operation............................................................................................... 83
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9.3. Parameter...........................................................................................................84
9.4. Configuration Registers.........................................................................................84
9.5. Interface Signals..................................................................................................84
9.6. Ethernet MDIO Core Revision History......................................................................85
10. Intel FPGA 16550 Compatible UART Core....................................................................86
10.1. Core Overview...................................................................................................86
10.2. Feature Description............................................................................................ 86
10.2.1. Unsupported Features.............................................................................87
10.2.2. Interface...............................................................................................87
10.2.3. General Architecture...............................................................................89
10.2.4. 16550 UART General Programming Flow Chart........................................... 89
10.2.5. Configuration Parameters........................................................................ 91
10.2.6. DMA Support......................................................................................... 91
10.2.7. FPGA Resource Usage............................................................................. 92
10.2.8. Timing and Fmax................................................................................... 92
10.2.9. Avalon-MM Slave....................................................................................93
10.2.10. Over-run/Under-run Conditions.............................................................. 94
10.2.11. Hardware Auto Flow-Control.................................................................. 95
10.2.12. Clock and Baud Rate Selection............................................................... 96
10.3. Software Programming Model.............................................................................. 96
10.3.1. Overview.............................................................................................. 96
10.3.2. Supported Features................................................................................ 96
10.3.3. Unsupported Features.............................................................................97
10.3.4. Configuration.........................................................................................97
10.3.5. 16550 UART API.................................................................................... 97
10.3.6. Driver Examples...................................................................................101
10.4. Address Map and Register Descriptions ...............................................................105
10.4.1. rbr_thr_dll...........................................................................................106
10.4.2. ier_dlh................................................................................................ 107
10.4.3. iir.......................................................................................................109
10.4.4. fcr......................................................................................................110
10.4.5. lcr...................................................................................................... 112
10.4.6. mcr.................................................................................................... 113
10.4.7. lsr...................................................................................................... 114
10.4.8. msr.................................................................................................... 116
10.4.9. scr..................................................................................................... 118
10.4.10. afr.................................................................................................... 119
10.4.11. tx_low...............................................................................................120
10.5. Intel FPGA 16550 Compatible UART Core Revision History......................................120
11. UART Core.................................................................................................................122
11.1. Core Overview................................................................................................. 122
11.2. Functional Description.......................................................................................122
11.2.1. Avalon-MM Slave Interface and Registers.................................................122
11.2.2. RS-232 Interface..................................................................................123
11.2.3. Transmitter Logic..................................................................................123
11.2.4. Receiver Logic......................................................................................123
11.2.5. Baud Rate Generation........................................................................... 124
11.3. Instantiating the Core....................................................................................... 124
11.3.1. Configuration Settings...........................................................................124
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11.4. Software Programming Model.............................................................................127
11.4.1. HAL System Library Support.................................................................. 127
11.4.2. Software Files...................................................................................... 131
11.4.3. Register Map........................................................................................131
11.4.4. Interrupt Behavior................................................................................136
11.5. UART Core Revision History............................................................................... 136
12. JTAG UART Core........................................................................................................ 138
12.1. Core Overview................................................................................................. 138
12.2. Functional Description.......................................................................................138
12.2.1. Avalon Slave Interface and Registers.......................................................139
12.2.2. Read and Write FIFOs........................................................................... 139
12.2.3. JTAG Interface..................................................................................... 139
12.2.4. Host-Target Connection......................................................................... 139
12.3. Configuration...................................................................................................140
12.3.1. Configuration Page............................................................................... 140
12.4. Software Programming Model.............................................................................141
12.4.1. HAL System Library Support.................................................................. 141
12.4.2. Software Files...................................................................................... 144
12.4.3. Accessing the JTAG UART Core via a Host PC............................................144
12.4.4. Register Map........................................................................................144
12.4.5. Interrupt Behavior................................................................................146
12.5. JTAG UART Core Revision History........................................................................147
13. Intel FPGA Avalon Mailbox Core................................................................................ 148
13.1. Core Overview................................................................................................. 148
13.2. Functional Description.......................................................................................148
13.2.1. Message Sending and Retrieval Process................................................... 149
13.2.2. Component Register Map.......................................................................149
13.3. Interface......................................................................................................... 151
13.3.1. Component Interface............................................................................ 151
13.3.2. Component Parameterization................................................................. 152
13.4. HAL Driver...................................................................................................... 153
13.4.1. Feature Description...............................................................................153
13.5. Intel FPGA Avalon Mailbox Core Revision History...................................................158
14. Intel FPGA Avalon Mutex Core.................................................................................. 159
14.1. Core Overview................................................................................................. 159
14.2. Functional Description.......................................................................................159
14.3. Configuration...................................................................................................160
14.4. Software Programming Model.............................................................................160
14.4.1. Software Files...................................................................................... 160
14.4.2. Hardware Access Routines..................................................................... 161
14.5. Mutex API....................................................................................................... 161
14.5.1. altera_avalon_mutex_is_mine()............................................................. 161
14.5.2. altera_avalon_mutex_first_lock()........................................................... 162
14.5.3. altera_avalon_mutex_lock()...................................................................162
14.5.4. altera_avalon_mutex_open()................................................................. 162
14.5.5. altera_avalon_mutex_trylock()...............................................................163
14.5.6. altera_avalon_mutex_unlock()............................................................... 163
14.6. Intel FPGA Avalon Mutex Core Revision History.....................................................163
Contents
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