library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;entity SSQ is
port(a,b,c,d,rst,op,clk,clk1:in std_logic; --a,bc,d代表1，2，3，4位选手
scan: out std_logic_vector(5 downto 0);--数码管动态扫描
dout: out std_logic_vector(7 downto 0)--数码管段码
);
end ;
architecture a of SSQ is
signal din,save,number:std_logic_vector(3 downto 0); --选手号码寄存器
signal wrong,right: std_logic_vector(3 downto 0); --正确与错误选手号码寄存器
signal dataout,stime: std_logic_vector(3 downto 0); --数据,时间寄存器
signal temp: std_logic_vector(2 downto 0); --显示器动态刷新计算器
signal enable,fff,kk,fft,noagain,sss,flag1: std_logic; --抢答器是能信号
signal time1:std_logic_vector(3 downto 0);
signal time2:std_logic_vector(3 downto 0);
begin
process(clk1)
begin
if clk1'event and clk1 ='1' then
if temp="101" then
temp<="000";
else
temp<=temp+1;
end if;
end if;
end process;
--动态扫描
process(temp,clk1)
begin
case temp is
when "000" => dataout<=wrong; scan<="000001";
when "001" => dataout<=time1; scan<="000010";
when "010" => dataout<=time2; scan<="000100";
when "011" => dataout<=right; scan<="001000";
when "100" => dataout<="0000"; scan<="010000";
when "101" => dataout<=stime; scan<="100000";
when others =>null;
end case;
end process;
-- scan<=not fscan;
--rst为清'0'位，
process(a,b,c,d,rst)
begin
din<=a&b&c&d;
if rst='1' then
enable<='1';
save<="0000";
elsif enable='0' then
null;
elsif enable='1' then
case din is
when "1110"=>save<="0001"; enable<='0';
when "1101"=>save<="0010"; enable<='0';
when "1011"=>save<="0011"; enable<='0';
